US6020230A
Expired / Lapsed
US
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Process to fabricate planarized deep-shallow trench isolation having upper and lower portions with oxidized semiconductor trench fill in the upper portion and semiconductor trench fill in the lower portion
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1998-04-22
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Granted: 2000-02-01
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Expires: 2018-04-22
Abstract
Abstract The method in the present invention is proposed for forming trench isolation in a semiconductor substrate. The method includes the steps as follows. At first, a pad layer is formed over the substrate. A first stacked layer is then formed over the pad layer. Next, a second stacked layer is formed over the first stacked layer. An opening is defined in the second stacked layer, the first stacked layer, and the pad layer. The opening extends down to the substrate. A portion of the substrate is then removed for forming an upper-half portion of a trench by using the second stacked layer as a mask. A sidewall structure is formed on the opening. Next, a portion of the substrate is removed for forming a lower-half portion of the trench by using the sidewall structure as a mask. The sidewall structure and the second stacked layer are removed. Following with the formation of a first insulating layer over the trench, a second insulating layer is formed over the first insulating layer and over the first stacked layer. A semiconductor layer is then formed over the second insulating layer. A portion of the semiconductor layer is oxidized for forming a third insulating layer. Finally, a filling layer is formed over the third insulating layer and the substrate is planarized for having a planar surface.
Inventors
- 👤 Shye-Lin Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 15:27
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0142; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
185 words
A method of forming trench isolation in a semiconductor substrate, said method comprising the steps of: forming a pad layer over said substrate; forming a first stacked layer over said pad layer; forming a second stacked layer over said first stacked layer; defining an opening in said second stacked layer, said first stacked layer, and said pad layer, said opening extending down to said substrate; removing a portion of said substrate for forming an upper-half portion of a trench by using said second stacked layer as a mask; forming a sidewall structure on said opening; removing a portion of said substrate for forming a lower-half portion of said trench by using said sidewall structure as a mask; removing said sidewall structure and said second stacked layer; forming a first insulating layer over said trench; forming a second insulating layer over said first insulating layer and over said first stacked layer; forming a semiconductor layer over said second insulating layer; oxidizing a portion of said semiconductor layer for forming a third insulating layer; forming a filling layer over said third insulating layer; and planarizing said substrate.
Claim 2
Independent Claim
185 words
A method of forming trench isolation in a semiconductor substrate, said method comprising the steps of: forming a pad layer over said substrate; forming a first stacked layer over said pad layer; forming a second stacked layer over said first stacked layer; defining an opening in said second stacked layer, said first stacked layer, and said pad layer, said opening extending down to said substrate; removing a portion of said substrate for forming an upper-half portion of a trench by using said second stacked layer as a mask; forming a sidewall structure on said opening; removing a portion of said substrate for forming a lower-half portion of said trench by using said sidewall structure as a mask; removing said sidewall structure and said second stacked layer; forming a first insulating layer over said trench; forming a second insulating layer over said first insulating layer and over said first stacked layer; forming a semiconductor layer over said second insulating layer; oxidizing a portion of said semiconductor layer for forming a third insulating layer; forming a filling layer over said third insulating layer; and planarizing said substrate.
Claim 3
Dependent Claim
20 words
The method of claim 1, wherein said pad layer comprises an oxide layer which is grown thermally from said substrate.
Claim 4
Dependent Claim
21 words
The method of claim 1, wherein said first stacked layer comprises a nitride layer which is formed by chemical vapor deposition.
Claim 5
Dependent Claim
19 words
The method of claim 1, wherein said second stacked layer comprises an oxide layer deposited by chemical vapor deposition.
Claim 6
Dependent Claim
17 words
The method of claim 1, wherein said opening is defined by a lithography and an etching process.
Claim 7
Dependent Claim
23 words
The method of claim 1, wherein said sidewall structure is an oxide sidewall structure formed by depositing and etching back an oxide layer.
Claim 8
Dependent Claim
21 words
The method of claim 1, wherein said first insulating layer comprises an oxide layer which is grown thermally from said substrate.
Claim 9
Dependent Claim
21 words
The method of claim 1, wherein said second insulating layer comprises an oxynitride layer which is formed by chemical vapor deposition.
Claim 10
Dependent Claim
22 words
The method of claim 1, wherein said semiconductor layer comprises an undoped amorphous silicon layer which is formed by chemical vapor deposition.
Claim 11
Dependent Claim
21 words
The method of claim 1, wherein said step of oxidizing said semiconductor layer is performed by a thermal steam oxidation process.
Claim 12
Dependent Claim
17 words
The method of claim 1, wherein said filling layer comprises a BPSG layer of a SOG layer.
Claim 13
Dependent Claim
17 words
The method of claim 1, wherein said step of planarizing said substrate is performed by chemical-mechanical polishing.
Claim 14
Independent Claim
250 words
A method of forming trench isolation in a semiconductor substrate, said method comprising the steps of: forming a pad layer over said substrate, said pad layer comprising a pad oxide layer which is grown thermally from said substrate; forming a first stacked layer over said pad layer, said first stacked layer comprising a nitride layer which is formed by chemical vapor deposition; forming a second stacked layer over said first stacked layer, said second stacked layer comprising a stacked oxide layer deposited by chemical vapor deposition; defining an opening in said second stacked layer, said first stacked layer, and said pad layer, said opening extending down to said substrate; removing a portion of said substrate for forming an upper-half portion of a trench by using said second stacked layer as a mask; forming a sidewall structure on said opening; removing a portion of said substrate for forming a lower-half portion of said trench by using said sidewall structure as a mask; removing said sidewall structure and said second stacked layer; forming a first insulating layer over said trench; forming a second insulating layer over said first insulating layer and over said first stacked layer, said second insulating layer comprising an oxynitride layer which is formed by chemical vapor deposition; forming a silicon layer over said second insulating layer; oxidizing a portion of said silicon layer for forming a third insulating layer by a thermal steam oxidation process; forming a filling layer over said third insulating layer; and planarizing said substrate.
Claim 15
Independent Claim
250 words
A method of forming trench isolation in a semiconductor substrate, said method comprising the steps of: forming a pad layer over said substrate, said pad layer comprising a pad oxide layer which is grown thermally from said substrate; forming a first stacked layer over said pad layer, said first stacked layer comprising a nitride layer which is formed by chemical vapor deposition; forming a second stacked layer over said first stacked layer, said second stacked layer comprising a stacked oxide layer deposited by chemical vapor deposition; defining an opening in said second stacked layer, said first stacked layer, and said pad layer, said opening extending down to said substrate; removing a portion of said substrate for forming an upper-half portion of a trench by using said second stacked layer as a mask; forming a sidewall structure on said opening; removing a portion of said substrate for forming a lower-half portion of said trench by using said sidewall structure as a mask; removing said sidewall structure and said second stacked layer; forming a first insulating layer over said trench; forming a second insulating layer over said first insulating layer and over said first stacked layer, said second insulating layer comprising an oxynitride layer which is formed by chemical vapor deposition; forming a silicon layer over said second insulating layer; oxidizing a portion of said silicon layer for forming a third insulating layer by a thermal steam oxidation process; forming a filling layer over said third insulating layer; and planarizing said substrate.
Claim 16
Dependent Claim
17 words
The method of claim 13, wherein said opening is defined by a lithography and an etching process.
Claim 17
Dependent Claim
23 words
The method of claim 13, wherein said sidewall structure is an oxide sidewall structure formed by depositing and etching back an oxide layer.
Claim 18
Dependent Claim
21 words
The method of claim 13, wherein said first insulating layer comprises an oxide layer which is grown thermally from said substrate.
Claim 19
Dependent Claim
22 words
The method of claim 13, wherein said silicon layer comprises an undoped amorphous silicon layer which is formed by chemical vapor deposition.
Claim 20
Dependent Claim
17 words
The method of claim 13, wherein said filling layer comprises a BPSG layer of a SOG layer.
Claim 21
Dependent Claim
17 words
The method of claim 13, wherein said step of planarizing said substrate is performed by chemical-mechanical polishing.
References Cited (Backward Citations)
US4810668A
Cited
US5474953A
Cited
US5246537A
Cited
US5433794A
Cited
US5496765A
Cited
US5445988A
Cited
US5679599A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2003-01-31 | 2003-08-02 | 2004-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-01-31 | 2007-08-02 | 2008-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-01-31 | 2011-08-02 | 2012-02-01 | $7700.00 | Window Closed / Lapsed |