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US4810668A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device element-isolation by oxidation of polysilicon in trench

Assignee: Toshiba Corp
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Filing: 1987-07-13
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Granted: 1989-03-07
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Expires: 2007-07-13
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Abstract

Abstract A method of manufacturing a semiconductor apparatus is disclosed, in which in the method of isolating elements, is improved. A groove is cut in a semiconductor substrate. Elements are isolated from each other by embedding an insulating material in the groove, in two divided portions. The time required for depositing an insulating material is reduced, thereby forming a uniform insulation layer on the semiconductor substrate. Since the insulating material can be etched in a shorter period of time than was previously required, the etching process can be more finely controlled. Since a field oxide layer is formed by oxidizing an insulation layer formed for the first time, the field oxide layer can be provided without oxidizing those portions of the semiconductor substrate which lie near the groove. Consequently, the seminconductor substrate can be free from crystalline defects.

Inventors

  • 👤 Takao Ito

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-02 20:01
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/10; H10W10/17; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10P50/644; H10P50/73; H10W10/01; H10W10/011; H10W10/014; H10W10/0142

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 211 words
A method of manufacturing a semiconductor apparatus, which comprises the steps of: forming a groove in a semiconductor substrate, said substrate having a region in which a plurality of active elements are formed, said groove being formed in an area other than said region; forming a first continuous insulation layer on the inner periphery of the groove and on the surface of the semiconductor substrate; forming a first polycrystalline silicon layer on the first insulation layer, said first polycrystalline silicon layer having such thickness that the groove is not completely filled; coating the first polycrystalline silicon layer with a second insulation layer; forming a second polycrystalline silicon layer on the second insulation layer, with a thickness sufficient to fill the groove; retaining the second polycrystalline silicon layer only in the groove; removing that portion of the first polycrystalline silicon layer which is positioned above that region of the semiconductor substrate and the first insulation layer in which active elements are formed; and oxidizing that portion of the first polycrystalline silicon layer which is formed over the semiconductor substrate and the first insulation layer in which no active elements are formed and the portions of the first and second polycrystalline silicon layers formed in the groove, thereby forming a field oxide layer.
Claim 2
Independent Claim 211 words
A method of manufacturing a semiconductor apparatus, which comprises the steps of: forming a groove in a semiconductor substrate, said substrate having a region in which a plurality of active elements are formed, said groove being formed in an area other than said region; forming a first continuous insulation layer on the inner periphery of the groove and on the surface of the semiconductor substrate; forming a first polycrystalline silicon layer on the first insulation layer, said first polycrystalline silicon layer having such thickness that the groove is not completely filled; coating the first polycrystalline silicon layer with a second insulation layer; forming a second polycrystalline silicon layer on the second insulation layer, with a thickness sufficient to fill the groove; retaining the second polycrystalline silicon layer only in the groove; removing that portion of the first polycrystalline silicon layer which is positioned above that region of the semiconductor substrate and the first insulation layer in which active elements are formed; and oxidizing that portion of the first polycrystalline silicon layer which is formed over the semiconductor substrate and the first insulation layer in which no active elements are formed and the portions of the first and second polycrystalline silicon layers formed in the groove, thereby forming a field oxide layer.
Claim 3
Dependent Claim 25 words
The method of manufacturing a semiconductor apparatus according to claim 1, wherein the first insulation layer contains an acidproof sublayer and a silicon oxide sublayer.
Claim 4
Dependent Claim 49 words
The method of manufacturing a semiconductor apparatus according to claim 1, wherein the second polycrystalline silicon layer is first retained only in the groove, and thereafter that portion of the second insulation layer which is retained on the surface of the semiconductor substrate except for the groove is removed.
Claim 5
Dependent Claim 29 words
The method of manufacturing a semiconductor apparatus according to claim 1, wherein the side wall of the groove is rendered perpendicular to the flat surface of the semiconductor substrate.
Claim 6
Dependent Claim 30 words
The method of manufacturing a semiconductor apparatus according to claim 1, wherein the side wall of the groove is rendered substantially perpendicular to the flat surface of the semiconductor substrate.
Claim 7
Dependent Claim 89 words
The method of manufacturing a semiconductor apparatus according to claim 1, wherein, before the formation of the groove in the semiconductor substrate, a first silicon oxide layer, a first silicon nitride layer, and a second silicon oxide layer used as an etching mask for the formation of the groove are deposited, in the order stated, on the surface of the semiconductor substrate; a photoresist layer is formed over all these layers; the photoresist layer is patterned; the three layers are selectively etched; and last the photoresist layer is removed.
Claim 8
Dependent Claim 34 words
The method of manufacturing a semiconductor apparatus according to claim 1, wherein the groove is formed in the semiconductor apparatus by means of anisotropic etching involving the use of the reactive ion etching method.
Claim 9
Dependent Claim 55 words
The method of manufacturing a semiconductor apparatus according to claim 1, wherein the process of retaining the second polycrystalline silicon layer only in the groove comprises the step of etching the second polycrystalline layer until that portion of the second insulation layer which is deposited on the flat surface of the semiconductor substrate is exposed.
Claim 10
Dependent Claim 25 words
The method of manufacturing a semiconductor apparatus according to claim 2, wherein the acidproof layer constituting the first insulation layer is a silicon nitride layer.
Claim 11
Dependent Claim 21 words
The method of manufacturing a semiconductor apparatus according to claim 1, wherein the second insulation layer is prepared from silicon nitride.
Claim 12
Dependent Claim 27 words
The method of manufacturing a semiconductor apparatus according to claim 1, wherein the first polycrystalline silicon layer is prepared by use of the chemical vapor deposition process.
Claim 13
Independent Claim 372 words
A method of manufacturing a semiconductor apparatus, which comprises the steps of: depositing a first silicon oxide layer, a first silicon nitride layer, and a second silicon oxide layer, in the order stated, on the surface of a semiconductor substrate, said semiconductor substrate having a region in which a plurality of active elements are formed; forming a photoresist layer over all of said first silicon oxide layer, said first silicon nitride layer and said second silicon oxide layer; patterning said photoeresist layer; etching the portions of said first silicon oxide layer, said first silicon nitride layer and said second silicon oxide layer not covered by said patterned photoresist layer; removing said photoresist layer; forming a groove in the semiconductor substrate in a portion of said substrate other than said region, said second silicon oxide layer being used as an etching mask for the formation of the groove; forming a first continuous insulation layer on the inner periphery of the groove and on the surface of the semiconductor substrate, the second silicon oxide layer is removed before the first insulation layer is formed on the inner peripheral wall of the groove, as well as over the surface of the semiconductor substrate; forming a third silicon oxide layer on the inner peripheral wall of the groove; removing the first silicon nitride layer and first silicon oxide layer; forming a first polycrystalline silicon layer on the first insulation layer, said first polycrystalline silicon layer having such thickness that the groove is not completely filled; coating the first polycrystalline silicon layer with a second insulation layer; forming a second polycrystalline silicon layer on the second insulation layer, with a thickness sufficient to fill the groove; retaining the second polycrystalline silicon layer only in the groove; removing that portion of the first polycrystalline silicon layer which is positioned above that region of the semiconductor substrate and the first insulation layer in which active elements are formed; and oxidizing that portion of the first polycrystalline silicon layer positioned above that region of the semiconductor substrate and the first insulation layer in which no active elements are formed and the portions of the first and second polycrystalline silicon layers formed in the groove, thereby forming a field oxide layer.
Claim 14
Independent Claim 372 words
A method of manufacturing a semiconductor apparatus, which comprises the steps of: depositing a first silicon oxide layer, a first silicon nitride layer, and a second silicon oxide layer, in the order stated, on the surface of a semiconductor substrate, said semiconductor substrate having a region in which a plurality of active elements are formed; forming a photoresist layer over all of said first silicon oxide layer, said first silicon nitride layer and said second silicon oxide layer; patterning said photoeresist layer; etching the portions of said first silicon oxide layer, said first silicon nitride layer and said second silicon oxide layer not covered by said patterned photoresist layer; removing said photoresist layer; forming a groove in the semiconductor substrate in a portion of said substrate other than said region, said second silicon oxide layer being used as an etching mask for the formation of the groove; forming a first continuous insulation layer on the inner periphery of the groove and on the surface of the semiconductor substrate, the second silicon oxide layer is removed before the first insulation layer is formed on the inner peripheral wall of the groove, as well as over the surface of the semiconductor substrate; forming a third silicon oxide layer on the inner peripheral wall of the groove; removing the first silicon nitride layer and first silicon oxide layer; forming a first polycrystalline silicon layer on the first insulation layer, said first polycrystalline silicon layer having such thickness that the groove is not completely filled; coating the first polycrystalline silicon layer with a second insulation layer; forming a second polycrystalline silicon layer on the second insulation layer, with a thickness sufficient to fill the groove; retaining the second polycrystalline silicon layer only in the groove; removing that portion of the first polycrystalline silicon layer which is positioned above that region of the semiconductor substrate and the first insulation layer in which active elements are formed; and oxidizing that portion of the first polycrystalline silicon layer positioned above that region of the semiconductor substrate and the first insulation layer in which no active elements are formed and the portions of the first and second polycrystalline silicon layers formed in the groove, thereby forming a field oxide layer.

References Cited (Backward Citations)

JPS5760851A Cited
US4356211A Cited
US4546538A Cited
US4700464A Cited
US4528047A Cited
US4621414A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-03-06 1992-09-05 1993-03-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-03-06 1996-09-05 1997-03-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-03-06 2000-09-05 2001-03-07 $7700.00 Window Closed / Lapsed

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