← Back to Patent Explorer
US6737333B2 Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device isolation structure and method of forming

Assignee: Texas Instruments Inc
•
Filing: 2002-06-20
•
Granted: 2004-05-18
•
Expires: 2022-06-20
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method for isolating semiconductor devices includes forming a first oxide layer outwardly from a semiconductor substrate, forming a first nitride layer outwardly from the first oxide layer, removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate to form a trench isolation region, forming a second oxide layer in the trench isolation region, forming a spin-on-glass region in the trench isolation region, annealing the spin-on-glass region, removing a portion of the spin-on-glass region to expose a shallow trench isolation region, and forming a third oxide layer in the shallow trench isolation region.

Inventors

  • 👤 Zhihao Chen
  • 👤 Douglas T. Grider
  • 👤 Freidoon Mehrad

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 06:09
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/10; H10W10/17

Claims Analysis

Total Claims: 14
Claim 1
Independent Claim 106 words
A method for isolating semiconductor devices, the method comprising: forming a first oxide layer outwardly from a semiconductor substrate; forming a first nitride layer outwardly from the first oxide layer; removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate to form a trench isolation region; forming a second oxide layer in the trench isolation region; forming a spin-on-glass region in the trench isolation region; annealing the spin-on-glass region; removing a portion of the spin-on-glass region to expose a shallow trench isolation region; and forming a third oxide layer in the shallow trench isolation region.
Claim 2
Independent Claim 106 words
A method for isolating semiconductor devices, the method comprising: forming a first oxide layer outwardly from a semiconductor substrate; forming a first nitride layer outwardly from the first oxide layer; removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate to form a trench isolation region; forming a second oxide layer in the trench isolation region; forming a spin-on-glass region in the trench isolation region; annealing the spin-on-glass region; removing a portion of the spin-on-glass region to expose a shallow trench isolation region; and forming a third oxide layer in the shallow trench isolation region.
Claim 3
Dependent Claim 31 words
The method of claim 1 , wherein the trench isolation region has a depth between approximately 0.7 microns and 1.3 microns and a width between approximately 0.1 microns and 0.13 microns.
Claim 4
Dependent Claim 25 words
The method of claim 1 , wherein the trench isolation region has a depth of approximately one micron and a width of approximately 0.12 microns.
Claim 5
Dependent Claim 62 words
The method of claim 1 , wherein annealing the spin-on-glass region comprises annealing the spin-on-glass region at a temperature between approximately 300° C. and 400° C. for a time period between approximately 15 and 30 minutes, and then annealing the spin-on-glass region at a temperature between approximately 900° C. and 1000° C. for a time period between approximately 5 and 10 minutes.
Claim 6
Dependent Claim 54 words
The method of claim 1 , wherein annealing the spin-on-glass region comprises annealing the spin-on-glass region at a temperature of approximately 400° C. for a time period of approximately 30 minutes, and then annealing the spin-on-glass region at a temperature of approximately 1000° C. for a time period between approximately 5 and 10 minutes.
Claim 7
Dependent Claim 22 words
The method of claim 1 , wherein the shallow trench isolation region has a depth between approximately 2000 Å and 2700 Å.
Claim 8
Dependent Claim 19 words
The method of claim 1 , wherein the shallow trench isolation region has a depth of approximately 2000 Å.
Claim 9
Dependent Claim 30 words
The method of claim 1 , wherein forming the second oxide layer in the trench isolation region comprises forming the second oxide layer with a thickness of approximately 150 Å.
Claim 10
Independent Claim 194 words
A method for isolating semiconductor devices, the method comprising: forming a first oxide layer outwardly from a semiconductor substrate; forming a first nitride layer outwardly from the first oxide layer; removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate to form a trench isolation region having a depth between approximately 0.7 microns and 1.3 microns and a width between approximately 0.1 microns and 0.13 microns; forming a second oxide layer in the trench isolation region; forming a spin-on-glass region in the trench isolation region; annealing the spin-on-glass region at a temperature between approximately 300° C. and 400° C. for a time period between approximately 15 and 30 minutes, and then annealing the spin-on-glass region at a temperature between approximately 900° C. and 1000° C. for a time period between approximately 5 and 10 minutes; removing a portion of the spin-on-glass region to expose a shallow trench isolation region having a depth between approximately 2000 Å and 2700 Å; forming a third oxide layer in the shallow trench isolation region; and polishing the third oxide layer by utilizing a chemical mechanical polishing technique.
Claim 11
Independent Claim 194 words
A method for isolating semiconductor devices, the method comprising: forming a first oxide layer outwardly from a semiconductor substrate; forming a first nitride layer outwardly from the first oxide layer; removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate to form a trench isolation region having a depth between approximately 0.7 microns and 1.3 microns and a width between approximately 0.1 microns and 0.13 microns; forming a second oxide layer in the trench isolation region; forming a spin-on-glass region in the trench isolation region; annealing the spin-on-glass region at a temperature between approximately 300° C. and 400° C. for a time period between approximately 15 and 30 minutes, and then annealing the spin-on-glass region at a temperature between approximately 900° C. and 1000° C. for a time period between approximately 5 and 10 minutes; removing a portion of the spin-on-glass region to expose a shallow trench isolation region having a depth between approximately 2000 Å and 2700 Å; forming a third oxide layer in the shallow trench isolation region; and polishing the third oxide layer by utilizing a chemical mechanical polishing technique.
Claim 12
Dependent Claim 18 words
The method of claim 9 , wherein the trench isolation region has a depth of approximately one micron.
Claim 13
Dependent Claim 54 words
The method of claim 9 , wherein annealing the spin-on-glass region comprises annealing the spin-on-glass region at a temperature of approximately 400° C. for a time period of approximately 30 minutes, and then annealing the spin-on-glass region at a temperature of approximately 1000° C. for a time period between approximately 5 and 10 minutes.
Claim 14
Dependent Claim 19 words
The method of claim 9 , wherein the shallow trench isolation region has a depth of approximately 2000 Å.

References Cited (Backward Citations)

JPS62106645A Cited
JPH03234041A Cited
US6214735B1 Cited
US5801082A Cited
US6020230A Cited
US6479369B1 Cited
US6417073B2 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2007-05-18 2007-11-17 2008-05-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2011-05-18 2011-11-17 2012-05-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2015-05-18 2015-11-17 2016-05-18 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag