US6724603B2
Expired / Lapsed
US
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Electrostatic discharge protection circuitry and method of operation
Assignee: NXP USA Inc
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Filing: 2002-08-09
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Granted: 2004-04-20
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Expires: 2022-08-09
Abstract
Abstract An Electrostatic Discharge (ESD) protection circuit ( 9 ) includes a plurality of I/O and power supply pad cells ( 22, 40 ) that comprise external pads ( 31, 41 ) and circuitry requiring ESD protection. The protection circuit includes an array of shunting devices ( 36, 46 ) coupled in parallel between an ESD bus ( 14 ) and a VSS bus ( 18 ) and distributed among the plurality of pad cells. One or more trigger circuits ( 50 ) control the shunting devices. ESD events are coupled from any stressed pad onto two separate buses: the ESD bus which routes the high ESD currents to the positive current electrodes of the multiple shunting devices, and a Boost bus ( 12 ) which controls the trigger circuits. During an ESD event, the trigger circuits drive the control electrodes of the shunting devices to a voltage level greater than possible with prior art circuits, thereby reducing the on-resistance of the shunting devices.
Inventors
- 👤 James W. Miller
- 👤 Geoffrey B. Hall
- 👤 Alexander Krasin
- 👤 Michael Stockinger
- 👤 Matthew D Akers
- 👤 Vishnu G. Kamat
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:32
CPC Classifications
H; H10; H10D; H10D84/00; H10D89/00; H10D89/60; H10D89/601; H10D89/921
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
198 words
An integrated circuit having an Electrostatic Discharge (ESD) circuitry comprising: a plurality of pads, wherein each of the plurality of pads is coupled to a first bus, a second bus, and a third bus; a plurality of pull-up circuits, wherein each of the plurality of pull-up circuits is coupled to each of the plurality of pads and the third bus; a plurality of shunting circuits, wherein: each of the plurality of pads is coupled to at least one of the plurality of shunting circuits via the first bus; the plurality of shunting circuits operate in parallel in response to an ESD event on at least one of the plurality of pads to provide ESD protection for the plurality of pads; and at least one of the plurality of shunting circuits is coupled to the first bus, a fourth bus and the second bus; and a trigger circuit comprising a transient detector circuit, said trigger circuit having a first terminal coupled to each of the plurality of pads via the third bus, a second terminal coupled to at least one of the plurality of shunting circuits via the fourth bus, and a third terminal coupled to the second bus.
Claim 2
Dependent Claim
198 words
An integrated circuit having an Electrostatic Discharge (ESD) circuitry comprising: a plurality of pads, wherein each of the plurality of pads is coupled to a first bus, a second bus, and a third bus; a plurality of pull-up circuits, wherein each of the plurality of pull-up circuits is coupled to each of the plurality of pads and the third bus; a plurality of shunting circuits, wherein: each of the plurality of pads is coupled to at least one of the plurality of shunting circuits via the first bus; the plurality of shunting circuits operate in parallel in response to an ESD event on at least one of the plurality of pads to provide ESD protection for the plurality of pads; and at least one of the plurality of shunting circuits is coupled to the first bus, a fourth bus and the second bus; and a trigger circuit comprising a transient detector circuit, said trigger circuit having a first terminal coupled to each of the plurality of pads via the third bus, a second terminal coupled to at least one of the plurality of shunting circuits via the fourth bus, and a third terminal coupled to the second bus.
Claim 3
Dependent Claim
58 words
The integrated circuit of claim 1 , wherein each of the plurality of shunting circuits comprises a transistor, wherein a control electrode of the transistor is coupled to the fourth bus, a first current electrode of the transistor is coupled to the second bus, and a second current electrode of the transistor is coupled to the first bus.
Claim 4
Dependent Claim
18 words
The integrated circuit of claim 2 , wherein each of the plurality of transistors is an NMOSFET transistor.
Claim 5
Dependent Claim
44 words
The integrated circuit of claim 1 , wherein each of the plurality of pull-up circuits further comprises a transistor having a first current electrode coupled to a predetermined one of the plurality of pads and a second current electrode coupled to the third bus.
Claim 6
Dependent Claim
40 words
The integrated circuit of claim 1 , wherein each of the plurality of pull-up circuits further comprises a diode having an anode coupled to a predetermined one of the plurality of pads and a cathode coupled to the third bus.
Claim 7
Dependent Claim
24 words
The integrated circuit of claim 1 , wherein the third bus and the first bus are coupled to each other via an equilibration circuit.
Claim 8
Dependent Claim
18 words
The integrated circuit of claim 1 , wherein the transient detector circuit comprises a Resistor-Capacitor (RC) transient detector.
Claim 9
Dependent Claim
19 words
The integrated circuit of claim 1 , wherein the plurality of pads comprises at least one Input/Output (I/O) pad.
Claim 10
Dependent Claim
30 words
The integrated circuit of claim 1 , wherein the plurality of shunting circuits are part of a continuous shunting network around a portion of a periphery of a semiconductor die.
Claim 11
Dependent Claim
46 words
The integrated circuit of claim 9 , further comprising a plurality of pad cells each comprising one of the plurality of pads and one of the plurality of pull-up circuits; and wherein the plurality of shunting circuits is physically located outside the plurality of pad cells.
Claim 12
Dependent Claim
22 words
The integrated circuit of claim 10 , wherein the plurality of shunting circuits are formed from a linear array of identical elements.
Claim 13
Dependent Claim
30 words
The integrated circuit of claim 9 , wherein a single shunting circuit spans a portion of a periphery of a semiconductor die occupied by two or more I/O pad cells.
Claim 14
Independent Claim
133 words
A method for compensating for electrostatic discharge (ESD) in an integrated circuit, the method comprising: placing a plurality of pads within the integrated circuit; coupling each of the plurality of pads to a first bus via a respective first diode device; coupling each of the plurality of pads to a second bus via a respective second diode device; coupling a transient detector circuit to the second bus and a third bus, the transient detector circuit having an output coupled to a fourth bus; physically placing a plurality of pull-up circuits each coupled to each of the plurality of pads and the third bus; and placing a plurality of shunting circuits, wherein at least one of the plurality of shunting circuits is coupled to the first bus, the fourth bus and the second bus.
Claim 15
Independent Claim
133 words
A method for compensating for electrostatic discharge (ESD) in an integrated circuit, the method comprising: placing a plurality of pads within the integrated circuit; coupling each of the plurality of pads to a first bus via a respective first diode device; coupling each of the plurality of pads to a second bus via a respective second diode device; coupling a transient detector circuit to the second bus and a third bus, the transient detector circuit having an output coupled to a fourth bus; physically placing a plurality of pull-up circuits each coupled to each of the plurality of pads and the third bus; and placing a plurality of shunting circuits, wherein at least one of the plurality of shunting circuits is coupled to the first bus, the fourth bus and the second bus.
Claim 16
Dependent Claim
18 words
The method of claim 13 further comprising: implementing each of the plurality of shunting circuits as discrete transistors.
Claim 17
Dependent Claim
69 words
The method of claim 13 , further comprising: implementing each of the plurality of shunting circuits as a transistor coupled to each of the plurality of pads having a body electrically coupled to a predetermined current electrode thereof and being controlled to be conductive in response to an ESD event at its respective pad to pull up voltage potential of the third bus in response to the ESD event.
Claim 18
Dependent Claim
41 words
The method of claim 13 , further comprising: implementing each of the plurality of pull up circuits as a diode having an anode coupled to a predetermined one of the plurality of pads and a cathode coupled to the third bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-04-20 | 2007-10-20 | 2008-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-04-20 | 2011-10-20 | 2012-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-04-20 | 2015-10-20 | 2016-04-20 | $7700.00 | Window Closed / Lapsed |