Integrated circuit apparatus including static electricity protection circuit

Claim 2

An integrated circuit apparatus comprising: at least first and second internal circuits respectively driven by at least first and second power sources; a plurality of input terminals provided for said first internal circuit; a plurality of output terminals provided for said second internal circuit in correspondence to said plurality of input terminals; first static electricity removing means provided between said plurality of input terminals and said first power source for electrically connecting each of said plurality of input terminals, which are supplied with static electricity with respect to said first power source as a reference, to said first power source for removing the applied static electricity; second static electricity removing means provided between said plurality of output terminals and said second power source for electrically connecting each of said plurality of output terminals, which are supplied with static electricity with respect to said second power source as a reference, to said second power source for removing the applied static electricity; and third static electricity removing means comprising MOS transistors provided between said first power source and said second power source, and when static electricity is applied to one of said plurality of input terminals with respect to said second power source as a reference or when static electricity is applied to one of said plurality of output terminals with respect to said first power source as a reference, said first power source and said second power source are electrically connected to remove the applied static electricity.

Claim 3

An integrated circuit apparatus according to claim 1, wherein said third static electricity removing means comprises a first static electricity removing path provided between a higher potential side of said first power source and a higher potential side of said second power source, and when positive static electricity is applied to one of said plurality of input terminals with respect to said first power source as a reference, the higher potential side of said first power source and the higher potential side of said second power source are electrically connected to remove said applied positive static electricity, and a second static electricity removing path provided between a lower potential side of said first power source and a lower potential side of said second power source, and when negative static electricity is applied to one of said plurality of input terminals with respect to said second power source as a reference or when negative static electricity is applied to one of said plurality of output terminals with respect to said first power source as a reference, the lower potential side of said first power source and the lower potential side of said second power source to remove the applied negative static electricity.

Claim 4

An integrated circuit apparatus according to claim 2, wherein said first static electricity removing means comprises first and second diode means provided for each of said plurality of input terminals and connected, to be reverse-biased, respectively between said plurality of input terminals and the higher potential side and the lower potential side of said first power source; and said second static electricity removing means comprises third and fourth diode means provide for each of said plurality of output terminals and connected, to be reverse-biased, respectively between said plurality of output terminals and the higher potential side and the lower potential side of said second power source.

Claim 5

An integrated circuit apparatus according to claim 2, wherein said first static electricity removing path comprises a first MOSFET including a control terminal and a first conduction terminal, connected to the higher potential side of said first power source, and a second conduction terminal connected to the higher potential side of said second power source; and said second static electricity removing path comprises a second MOSFET including a control terminal and a second conduction terminal, connected to the lower potential side of said first power source, and a second conduction terminal connected to the lower potential side of said second power source.

Claim 6

An integrated circuit apparatus according to claim 4, wherein said first and second MOSFETs each comprise an enhancement type N channel MOS transistor.

Claim 7

An integrated circuit apparatus according to claim 4, wherein said first and second MOSFETs each comprise an enhancement type P channel MOS transistor.

Claim 8

An integrated circuit apparatus comprising: first and second internal circuits provided respectively for corresponding first and second power sources; a first higher potential side terminal and a first lower potential side terminal for connecting said first power source to said first internal circuit; a second higher potential side terminal and a second lower potential side terminal for connecting said second power source to said second internal circuit; a plurality of input terminals connected to said first internal circuit for receiving an input signal to said first internal circuit; a plurality of output terminals connected to said second internal circuit for receiving an output signal from said second internal circuit in correspondence to said plurality of input terminals; a plurality of first diodes connected between each of said plurality of input terminals and said first higher potential side terminal; a plurality of second diodes connected between each of said plurality of input terminals and said first lower potential side terminal; a plurality of third diodes connected between each of said plurality of output terminals and said second higher potential side terminal; a plurality of fourth diodes connected between each of said plurality of output terminals and said second lower potential side terminal; a first N channel MOS transistor having a gate and a drain connected to said first higher potential side terminal and a source connected to said second higher potential side terminal; and a second N channel MOS transistor having a gate and a drain connected to said first lower potential side terminal and a source connected to said second lower potential side terminal, said first and second N channel MOS transistors being enhancement type transistors, said first lower potential side terminal being coupled to a ground potential of said first power source, and said second lower potential side terminal being coupled to a ground potential of said second power source.

Claim 9

An integrated circuit apparatus comprising: first and second internal circuits provided respectively for corresponding first and second power sources; a first higher potential side terminal and a first lower potential side terminal for connecting said first power source to said first internal circuit; a second higher potential side terminal and a second lower potential side terminal for connecting said second power source to said second internal circuit; a plurality of input terminals connected to said first internal circuit for receiving an input signal to said first internal circuit; a plurality of output terminals connected to said second internal circuit for receiving an output signal from said second internal circuit in correspondence to said plurality of input terminals; a plurality of first diodes connected between each of said plurality of input terminals and said first higher potential side terminal; a plurality of second diodes connected between each of said plurality of input terminals and said first lower potential side terminal; a plurality of third diodes connected between each of said plurality of output terminals and said second higher potential side terminal; a plurality of fourth diodes connected between each of said plurality of output terminals and said second lower potential side terminal; a first N channel MOS transistor having a gate and a drain connected to said first higher potential side terminal and a source connected to said second higher potential side terminal; and a second N channel MOS transistor having a gate and a drain connected to said first lower potential side terminal and a source connected to said second lower potential side terminal, said first and second N channel MOS transistors being enhancement type transistors, said first lower potential side terminal being coupled to a ground potential of said first power source, and said second lower potential side terminal being coupled to a ground potential of said second power source.

Claim 10

An integrated circuit apparatus according to claim 1, wherein the potential on a higher potential side of said first power source is different than the potential on a higher potential side of said second power source and the potential on a lower potential side of said first power source is different than the potential on a lower potential side of said second power source.

Claim 11

An integrated circuit apparatus according to claim 7, further comprising: a first static electricity removing path provided between said first higher potential side terminal and said second higher potential side terminal, and when positive static electricity is applied to only one of said plurality of input terminals with respect to said second power source as a reference or when positive static electricity is applied to one of said plurality of output terminals with respect to said first power source as a reference, said first higher potential side and said second higher potential side are electrically connected to remove said applied positive static electricity; and a second static electricity removing path provided between said first lower potential side terminal and said second higher potential side terminal, and when negative static electricity is applied to one of said plurality of input terminals with respect to said second power source as a reference or when negative static electricity is applied to one of said plurality of output terminals with respect to said first power source as a reference, said first lower potential side terminal and said second lower potential side terminal are electrically connected to remove the applied negative static electricity.

Claim 12

An integrated circuit apparatus according to claim 9, wherein each of said plurality of first diodes and each corresponding one of said plurality of second diodes are connected to be reverse-biased between said plurality of input terminals and said first higher and lower potential side terminals and each of said plurality of third diodes and each corresponding one of said plurality of fourth diodes are connected to be reverse-biased between said plurality of output terminals and said second higher and lower potential side terminals.

Claim 13

An integrated circuit apparatus according to claim 7, wherein the potential on said first higher potential side terminal is different than the potential on said second higher potential side terminal and the potential on said first lower potential side terminal is different than the potential on said second lower potential side terminal.