US5515232A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Static protection circuit for a semiconductor integrated circuit device
Assignee: NXP USA Inc
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Filing: 1994-09-22
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Granted: 1996-05-07
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Expires: 2014-09-22
Abstract
Abstract A static protection circuit for a semiconductor integrated circuit device which provides static protection for an integrated circuit driven on multiple different power supply voltages is provided. The static protection circuit comprises a transistor having its two controlled terminals connected to each of the power supply lines and a GND line, respectively, and its control line connected to one of said controlled terminals; and a transistor having its controlled terminals connected to each of said power supply lines and its control terminal to which a nonconductive voltage is applied.
Inventors
- 👤 Hidetaka Fukazawa
- 👤 Satoshi Sekine
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:29
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
136 words
A static protection circuit for a semiconductor integrated circuit device, including at least first and second power supply lines that supply different power supply voltages and a GND line, said circuit comprising: a first transistor having two controlled terminals and a control terminal, the controlled terminals connected to the first power supply line and said GND line, respectively, and the control terminal connected to one of said controlled terminals; and a second transistor having two controlled terminals and a control terminal, the controlled terminals connected to the second power supply line and said GND line, respectively, and the control terminal connected to one of said controlled terminals; and a third transistor having controlled terminals connected to each of said first and second power supply lines, and a control terminal to which a nonconductive voltage is applied.
Claim 2
Dependent Claim
136 words
A static protection circuit for a semiconductor integrated circuit device, including at least first and second power supply lines that supply different power supply voltages and a GND line, said circuit comprising: a first transistor having two controlled terminals and a control terminal, the controlled terminals connected to the first power supply line and said GND line, respectively, and the control terminal connected to one of said controlled terminals; and a second transistor having two controlled terminals and a control terminal, the controlled terminals connected to the second power supply line and said GND line, respectively, and the control terminal connected to one of said controlled terminals; and a third transistor having controlled terminals connected to each of said first and second power supply lines, and a control terminal to which a nonconductive voltage is applied.
Claim 3
Dependent Claim
40 words
A static protection circuit for a semiconductor integrated circuit device according to claim 1, wherein each of said first, second, and third transistors comprises the same type of transistor as used in circuit elements of said semiconductor integrated circuit device.
Claim 4
Dependent Claim
98 words
A static protection circuit for a semiconductor integrated circuit device according to claim 1, wherein each of said first, second, and third transistors comprises an N-channel FET, gate and source terminals of said first and second transistors are connected to each other, said source terminal and a drain terminal of said first and second transistors are connected to each of said power supply lines and said GND line, respectively, source and drain terminals of said third transistor are connected to said power supply lines, while a gate terminal of said third transistor is connected to said GND line.
Claim 5
Dependent Claim
98 words
A static protection circuit for a semiconductor integrated circuit device according to claim 1, wherein each of said first, second, and third transistors comprises a bipolar transistor; base and emitter terminals of said first and second transistors are connected to each other, said emitter terminal and a collector terminal of said first and second transistors are connected to each of said power supply lines and said GND line, respectively, emitter and collector terminals of said third transistor are connected to said power supply lines, while a base terminal of said third transistor is connected to said GND line.
References Cited (Backward Citations)
US4736271A
Cited
US5034845A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-07 | 1999-11-06 | 2000-05-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-07 | 2003-11-06 | 2004-05-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-07 | 2007-11-06 | 2008-05-07 | $7700.00 | Window Closed / Lapsed |