Patent US6709926B2 successfully refreshed from Google Patents.
US6709926B2
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US
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High performance logic and high density embedded dram with borderless contact and antispacer
Assignee: International Business Machines Corp
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Filing: 2002-05-31
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Granted: 2004-03-23
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Expires: 2022-05-31
Abstract
Abstract An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature size, and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.
Inventors
- 👤 Dureseti Chidambarrao
- 👤 Omer H. Dokumaci
- 👤 Bruce Bennett Doris
- 👤 Oleg Gluschenkov
- 👤 Rajarao Jammy
- 👤 Jack Allan Mandelman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:09
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10B12/053; H10B12/09; H10B12/03; H10B12/038; H10B12/0383; H10B12/30; H10B12/48; H10B12/488
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
131 words
A method of making an integrated circuit including steps of forming a dielectric layer on a semiconductor substrate, said dielectric layer including a gate dielectric region, forming a polysilicon layer on said dielectric layer and said gate dielectric region, removing said polysilicon layer in an array area of said integrated circuit, forming a plurality of layers including an insulator material layer on a remaining portion of said polysilicon layer and on portions of said gate dielectric such that recesses remain where polysilicon has been removed in said removing step, forming a mask in said recesses, removing said plurality of layers and said mask to a surface of said polysilicon in accordance with said mask, patterning said polysilicon and a remaining portion of said plurality of layers, and completing said integrated circuit.
Claim 2
Independent Claim
131 words
A method of making an integrated circuit including steps of forming a dielectric layer on a semiconductor substrate, said dielectric layer including a gate dielectric region, forming a polysilicon layer on said dielectric layer and said gate dielectric region, removing said polysilicon layer in an array area of said integrated circuit, forming a plurality of layers including an insulator material layer on a remaining portion of said polysilicon layer and on portions of said gate dielectric such that recesses remain where polysilicon has been removed in said removing step, forming a mask in said recesses, removing said plurality of layers and said mask to a surface of said polysilicon in accordance with said mask, patterning said polysilicon and a remaining portion of said plurality of layers, and completing said integrated circuit.
Claim 3
Dependent Claim
17 words
A method as recited in claim 1 , including a further step of planarizing said dielectric layer.
Claim 4
Dependent Claim
16 words
A method as recited in claim 2 , wherein said planarizing step is performed by polishing.
Claim 5
Dependent Claim
30 words
A method as recited in claim 1 , wherein said plurality of layers includes a diffusion barrier and a metal conductor layer and said step of patterning forms discrete conductors.
Claim 6
Dependent Claim
37 words
A method as recited in claim 4 including the further steps of placing mask material between portions of said polysilicon material patterned by said patterning step, implanting impurities into said polysilicon in accordance with said mask material.
Claim 7
Dependent Claim
36 words
A method as recited in claim 5 , including the further steps of forming a silicide on a surface of said portions of said polysilicon material while preventing formation of a silicide from said discrete conductors.
Claim 8
Dependent Claim
19 words
A method as recited in claim 4 , including the further step of oxidizing surfaces of said patterned polysilicon.
Claim 9
Dependent Claim
26 words
A method as recited in claim 7 , including the further step of removing oxide on sides of said patterned polysilicon formed by said oxidizing step.
Claim 10
Dependent Claim
28 words
A method as recited in claim 8 , including the further step of forming a sidewall on sides of said patterned silicon where said oxide has been removed.
Claim 11
Dependent Claim
27 words
A method as recited in claim 7 , including the further step of forming a sidewall over a portion of said oxide formed by said oxidizing step.
Claim 12
Dependent Claim
21 words
A method as recited in claim 1 , wherein said step of forming a mask includes application of a spin-on material.
Claim 13
Dependent Claim
17 words
A method as recited in claim 11 , including the further step of planarizing said spin-on material.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-03-23 | 2007-09-22 | 2008-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-03-23 | 2011-09-22 | 2012-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-03-23 | 2015-09-22 | 2016-03-23 | $7700.00 | Window Closed / Lapsed |