US6548871B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer
Assignee: Renesas Electronics Corp
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Filing: 2000-04-05
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Granted: 2003-04-15
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Expires: 2020-04-05
Abstract
Abstract Two source/drain regions ( 20 ) belonging to separate elements which are adjacent to each other are connected through a metal layer ( 14 ) having the same height as a height of a metal layer ( 10 ) forming a part of a gate electrode. In a manufacturing process, an insulating layer ( 8 ) is made of other material than and inserted between two insulating layers ( 7 ) and ( 16 ). The two insulating layers ( 7 ) and ( 16 )function as molds for burying the metal layers ( 10 ), ( 14 ) and ( 15 ) therein and made of the same material. The metal layer ( 14 ) can therefore be formed at the same height as the height of the metal layer ( 10 ). Accordingly, portions to be connected through a wiring which are provided at a comparatively short distance are connected while reducing a wiring capacity.
Inventors
- 👤 Katsuyuki Horita
- 👤 Takashi Kuroi
- 👤 Yasuyoshi Itoh
- 👤 Katsuomi Shiozawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:17
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0149; H10D84/02; H10D84/03; H10D84/038; H10W20/071; H10W20/081; H10W20/084; H10W20/086; H10W20/20; H10W20/40; H10D64/00; H10D64/01; H10D64/017
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
331 words
A semiconductor device comprising: a) a semiconductor substrate having a main surface; and b) a plurality of element regions set along said main surface of said semiconductor substrate, each of said element regions including: a channel region selectively provided in said main surface; a pair of source/drain regions selectively provided in said main surface with said channel region interposed therebetween; a gate insulating film provided on said channel region; a conductive layer provided on said gate insulating film; a first insulating layer which has a first opening selectively penetrating from an upper surface of said first insulating layer to a lower surface of said first insulating layer over a surface of said pair of source/drain regions, said first insulating layer accommodating said conductive layer; a second insulating layer provided on said first insulating layer and formed of a material different from a material of said first insulating layer, the second insulating layer selectively defining a second opening penetrating from an upper surface of said second insulating layer to a lower surface of said second insulating layer so as to communicate with said first opening and a surface of said conductive layer; a third insulating layer provided on said second insulating layer and formed of a material different from said material of said second insulating layer, said third insulating layer selectively defining a third opening which is opened to include said second opening in said second insulating layer, said third opening penetrating from an upper surface of said third insulating layer to a lower surface of said third insulating layer so as to communicate with said first and second openings; and a metal layer, buried in said first, second and third openings, the metal layer including: (1) a gate upper electrode provided on said conductive layer; and (2) a wiring layer electrically connected to wiring layers in other of said element regions; wherein an upper surface of said first insulating layer is arranged on a level with that of said conductive layer.
Claim 2
Dependent Claim
331 words
A semiconductor device comprising: a) a semiconductor substrate having a main surface; and b) a plurality of element regions set along said main surface of said semiconductor substrate, each of said element regions including: a channel region selectively provided in said main surface; a pair of source/drain regions selectively provided in said main surface with said channel region interposed therebetween; a gate insulating film provided on said channel region; a conductive layer provided on said gate insulating film; a first insulating layer which has a first opening selectively penetrating from an upper surface of said first insulating layer to a lower surface of said first insulating layer over a surface of said pair of source/drain regions, said first insulating layer accommodating said conductive layer; a second insulating layer provided on said first insulating layer and formed of a material different from a material of said first insulating layer, the second insulating layer selectively defining a second opening penetrating from an upper surface of said second insulating layer to a lower surface of said second insulating layer so as to communicate with said first opening and a surface of said conductive layer; a third insulating layer provided on said second insulating layer and formed of a material different from said material of said second insulating layer, said third insulating layer selectively defining a third opening which is opened to include said second opening in said second insulating layer, said third opening penetrating from an upper surface of said third insulating layer to a lower surface of said third insulating layer so as to communicate with said first and second openings; and a metal layer, buried in said first, second and third openings, the metal layer including: (1) a gate upper electrode provided on said conductive layer; and (2) a wiring layer electrically connected to wiring layers in other of said element regions; wherein an upper surface of said first insulating layer is arranged on a level with that of said conductive layer.
Claim 3
Dependent Claim
57 words
The semiconductor device according to claim 1 , further comprising: a fourth insulating layer provided under said first insulating layer, selectively defining a fourth opening formed under said first opening and having said conductive layer and said metal layer buried therein and is formed of a material different from materials of said first and third insulating layers.
Claim 4
Dependent Claim
24 words
The semiconductor device according to claim 1 , wherein said first insulating layer and said third insulating layer are formed of the same material.
Claim 5
Dependent Claim
24 words
The semiconductor device according to claim 2 , wherein said second insulating layer and said fourth insulating layer are formed of the same material.
Claim 6
Dependent Claim
41 words
The semiconductor device according to claim 1 , further comprising: an element isolating film which is selectively formed in an area between said element regions in said main surface; wherein said conductive layer is also provided on said element isolating film.
Claim 7
Dependent Claim
19 words
The semiconductor device according to claim 1 , wherein a material of said conductive layer is a polycrystalline semiconductor.
Claim 8
Dependent Claim
45 words
The semiconductor device according to claim 1 , wherein: said semiconductor substrate is a single crystal substrate including silicon as a base material, materials of said first and third insulating layers are silicon oxide, and a material of said second insulating layer is silicon nitride.
Claim 9
Dependent Claim
22 words
The semiconductor device according to claim 1 , wherein: the wiring layer extends to the same height as the gate upper electrode.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-04-14 | 2006-10-14 | 2007-04-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-04-14 | 2010-10-14 | 2011-04-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-04-14 | 2014-10-14 | 2015-04-15 | $7700.00 | Window Closed / Lapsed |