Semiconductor device having both memory and logic circuit and its manufacture

Claim 2

A semiconductor device comprising: a semiconductor substrate having a first area and a second area defined on a principal surface of the semiconductor substrate; a plurality of memory cells disposed in the first area of said semiconductor substrate, each memory cell including a first MISFET and a capacitor, and a gate electrode of each first MISFET having a first impurity concentration; and a plurality of second MISFET's disposed in the second area of said semiconductor substrate, each second MISFET having a conductivity type same as a conductivity type of the first MISFET and a gate electrode of each second MISFET having a second impurity concentration lower than the first impurity concentration.

Claim 3

A semiconductor device according to claim 1 , wherein an upper surface of the gate electrode of each second MISFET and upper surfaces of source/drain regions thereof are formed with a metal silicide film, and an upper surface of the gate electrode of each first MISFET and upper surfaces of source/drain regions thereof are not formed with a metal silicide film.

Claim 4

A semiconductor device comprising: a semiconductor substrate having a first area and a second area defined on a principal surface of the semiconductor substrate, and element separation structures formed on surfaces of the second area and the first area; a plurality of memory cells disposed on said semiconductor substrate in the first area, each memory cell including a first MISFET and a capacitor and a gate electrode of the first MISFET having a first layer structure; a plurality of second MISFET's disposed on said semiconductor substrate in the second area, each second MISFET having a same conductivity type as a conductivity type of the first MISFET and a gate of each second MISFET having a second layer structure; and a capacitor disposed on the element separation structure in the second area, the capacitor having a lower electrode, a capacitor dielectric film, and an upper electrode stacked in this order, wherein the upper electrode has the first layer structure and the lower electrode has the second layer structure.

Claim 5

A semiconductor device comprising: a semiconductor substrate having a first area and a second area defined on a principal surface of the semiconductor substrate, and element separation structures formed on surfaces of the second area and the first area; a plurality of memory cells disposed on said semiconductor substrate in the first area, each memory cell including a first MISFET and a capacitor and a gate electrode of the first MISFET having a first layer structure; a plurality of second MISFET's disposed on said semiconductor substrate in the second area, each second MISFET having a same conductivity type as a conductivity type of the first MISFET and a gate of each second MISFET having a second layer structure; and a capacitor disposed on the element separation structure in the second area, the capacitor having a lower electrode, a capacitor dielectric film, and an upper electrode stacked in this order, wherein the upper electrode has the first layer structure and the lower electrode has the second layer structure.

Claim 6

A semiconductor device comprising: MISFET's formed on a surface of a semiconductor substrate, each MISFET including source/drain regions and a gate electrode disposed above a channel region between the source/drain regions; a cover insulating film made of sulating material and covering an upper and side wall of the gate electrode; a conductive pad disposed covering a corresponding upper surface of the source/drain regions and corresponding side wall of said cover insulating films; an interlayer insulating film disposed over the semiconductor substrate and covering said pad and said MISFET's; a contact hole formed in said interlayer insulating film at a position included by said pad as viewed along a direction normal to the semiconductor substrate; and a capacitor formed on said interlayer insulating film, one electrode of said capacitor being connected via said contact hole to said pad.

Claim 7

A semiconductor device comprising: MISFET's formed on a surface of a semiconductor substrate, each MISFET including source/drain regions and a gate electrode disposed above a channel region between the source/drain regions; a cover insulating film made of sulating material and covering an upper and side wall of the gate electrode; a conductive pad disposed covering a corresponding upper surface of the source/drain regions and corresponding side wall of said cover insulating films; an interlayer insulating film disposed over the semiconductor substrate and covering said pad and said MISFET's; a contact hole formed in said interlayer insulating film at a position included by said pad as viewed along a direction normal to the semiconductor substrate; and a capacitor formed on said interlayer insulating film, one electrode of said capacitor being connected via said contact hole to said pad.

Claim 8

A semiconductor device comprising: a semiconductor substrate having a first area and a second area defined on a principal surface of the semiconductor substrate; an element separation structure formed on said semiconductor substrate in a border area between the first area and the second area; an interconnect wiring disposed on said element separation structure; a DRAM circuit formed on the semiconductor substrate in the first area, wherein the DRAM circuit includes a plurality of memory cells and bit lines, each memory cell has a pair of MISFET and a capacitor, one electrode of the capacitor is connected to one region of source/drain regions of a corresponding MISFET, the bit line interconnects the other regions of source/drain regions of MISFET's of some memory cells, the bit line extends near a border line between the first area and the second area, and the bit line is disposed on a layer higher than the interconnect wiring and connected thereto; an interlayer insulating film covering said DRAM circuit and the second area; a contact hole formed through said interlayer insulating film, a bottom of said contact hole being a partial upper surface of said interconnect wiring; and an upper wiring disposed on said interlayer insulating film, said upper wiring being connected via said contact hole to said interconnect wiring and extending in the second area.

Claim 9

A semiconductor device comprising: a semiconductor substrate having a first area and a second area defined on a principal surface of the semiconductor substrate; an element separation structure formed on said semiconductor substrate in a border area between the first area and the second area; an interconnect wiring disposed on said element separation structure; a DRAM circuit formed on the semiconductor substrate in the first area, wherein the DRAM circuit includes a plurality of memory cells and bit lines, each memory cell has a pair of MISFET and a capacitor, one electrode of the capacitor is connected to one region of source/drain regions of a corresponding MISFET, the bit line interconnects the other regions of source/drain regions of MISFET's of some memory cells, the bit line extends near a border line between the first area and the second area, and the bit line is disposed on a layer higher than the interconnect wiring and connected thereto; an interlayer insulating film covering said DRAM circuit and the second area; a contact hole formed through said interlayer insulating film, a bottom of said contact hole being a partial upper surface of said interconnect wiring; and an upper wiring disposed on said interlayer insulating film, said upper wiring being connected via said contact hole to said interconnect wiring and extending in the second area.

Claim 10

A semiconductor device comprising: a semiconductor substrate having a memory cell area, in which a memory circuit is formed, and a logic circuit area, in which a logic circuit connected with said memory circuit through a wiring is formed, defined on a principal surface of the semiconductor substrate; a plurality of memory cells disposed in the memory cell area of said semiconductor substrate, each memory cell including a first MISFET with a gate electrode and a capacitor, and the gate electrode of each first MISFET having a first impurity concentration; and a plurality of second MISFET's disposed in the logic circuit area of said semiconductor substrate, each second MISFET having a gate electrode and a conductivity type same as a conductivity type of the first MISFET and the gate electrode of each second MISFET having a second impurity concentration lower than the first impurity concentration.

Claim 11

A semiconductor device comprising: a semiconductor substrate having a memory cell area, in which a memory circuit is formed, and a logic circuit area, in which a logic circuit connected with said memory circuit through a wiring is formed, defined on a principal surface of the semiconductor substrate; a plurality of memory cells disposed in the memory cell area of said semiconductor substrate, each memory cell including a first MISFET with a gate electrode and a capacitor, and the gate electrode of each first MISFET having a first impurity concentration; and a plurality of second MISFET's disposed in the logic circuit area of said semiconductor substrate, each second MISFET having a gate electrode and a conductivity type same as a conductivity type of the first MISFET and the gate electrode of each second MISFET having a second impurity concentration lower than the first impurity concentration.

Claim 12

A semiconductor device comprising: a semiconductor substrate having a memory cell area, in which a memory circuit is formed, and a logic circuit area, in which a logic circuit connected with said memory circuit through a wiring is formed, defined on a principal surface of the semiconductor substrate, and element separation structures formed on surfaces of the logic circuit area and the memory cell area; a plurality ofmemory cells disposed on said semiconductor substrate in the memory cell area, each memory cell including a first MISFET with a gate electrode and a capacitor, and the gate electrode of the first MISFET having a lamination structure; a plurality of second MISFET's disposed on said semiconductor substrate in the logic circuit area, each second MISFET having a gate electrode and a same conductivity type as a conductivity type of the first MISFET; and a capacitor disposed on the element separation structure in the logic circuit area, the capacitor having a lower electrode, a capacitor dielectric film, and an upper electrode stacked in this order, wherein the upper electrode has a same lamination structure as the gate electrode of said first MISFET and the lower electrode consists of a same material as the gate electrode of said second MISFET.

Claim 13

A semiconductor device comprising: a semiconductor substrate having a memory cell area, in which a memory circuit is formed, and a logic circuit area, in which a logic circuit connected with said memory circuit through a wiring is formed, defined on a principal surface of the semiconductor substrate, and element separation structures formed on surfaces of the logic circuit area and the memory cell area; a plurality ofmemory cells disposed on said semiconductor substrate in the memory cell area, each memory cell including a first MISFET with a gate electrode and a capacitor, and the gate electrode of the first MISFET having a lamination structure; a plurality of second MISFET's disposed on said semiconductor substrate in the logic circuit area, each second MISFET having a gate electrode and a same conductivity type as a conductivity type of the first MISFET; and a capacitor disposed on the element separation structure in the logic circuit area, the capacitor having a lower electrode, a capacitor dielectric film, and an upper electrode stacked in this order, wherein the upper electrode has a same lamination structure as the gate electrode of said first MISFET and the lower electrode consists of a same material as the gate electrode of said second MISFET.

Claim 14

A semiconductor device comprising: a semiconductor substrate having a memory cell area and a logic circuit area defined on a principal surface of the semiconductor substrate; an element separation structure formed on said semiconductor substrate in a border area between the memory cell area and the logic circuit area; an interconnect wiring disposed on said element separation structure; a memory circuit formed on the semiconductor substrate in the memory cell area, wherein the memory circuit includes a plurality of memory cells and bit lines, each memory has a pair of MISFET and capacitor, one electrode of the capacitor is connected to one region of source/drain regions of a corresponding MISFET, the bit line interconnects the other regions of source/drain regions of MISFET's of some memory cells, the bit line extends near to a border line between the memory cell area and the logic circuit area, and the bit line is disposed on a layer higher than the interconnect wiring and connected thereto; an interlayer insulating film covering said memory circuit and the logic circuit area; a contact hole formed through said interlayer insulating film, a bottom of said contact hole being a partial upper surface of said interconnect wiring; and an upper wiring disposed on said interlayer insulating film, said upper wiring being connected via said contact hole to said interconnect wiring and being connected to a logic circuit extending in the logic circuit area.

Claim 15

A semiconductor device comprising: a semiconductor substrate having a memory cell area and a logic circuit area defined on a principal surface of the semiconductor substrate; an element separation structure formed on said semiconductor substrate in a border area between the memory cell area and the logic circuit area; an interconnect wiring disposed on said element separation structure; a memory circuit formed on the semiconductor substrate in the memory cell area, wherein the memory circuit includes a plurality of memory cells and bit lines, each memory has a pair of MISFET and capacitor, one electrode of the capacitor is connected to one region of source/drain regions of a corresponding MISFET, the bit line interconnects the other regions of source/drain regions of MISFET's of some memory cells, the bit line extends near to a border line between the memory cell area and the logic circuit area, and the bit line is disposed on a layer higher than the interconnect wiring and connected thereto; an interlayer insulating film covering said memory circuit and the logic circuit area; a contact hole formed through said interlayer insulating film, a bottom of said contact hole being a partial upper surface of said interconnect wiring; and an upper wiring disposed on said interlayer insulating film, said upper wiring being connected via said contact hole to said interconnect wiring and being connected to a logic circuit extending in the logic circuit area.