US6686637B1
Expired / Lapsed
US
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Gate structure with independently tailored vertical doping profile
Assignee: GlobalFoundries US Inc
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Filing: 2002-11-21
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Granted: 2004-02-03
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Expires: 2022-11-21
Abstract
Abstract A gate structure for a semiconductor transistor is disclosed. In an exemplary embodiment, the gate structure includes a lower polysilicon region doped at a first dopant concentration and an upper polysilicon region doped at a second concentration, with the second concentration being different than the first concentration. A conductive barrier layer is disposed between the lower and the upper polysilicon regions, wherein the conductive barrier layer prevents diffusion of impurities between the lower and the upper polysilicon regions.
Inventors
- 👤 Omer Dokumaci
- 👤 Bruce B. Doris
- 👤 Oleg Gluschenkov
- 👤 Jack A. Mandelman
- 👤 Carl Radens
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:08
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/017; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10P; H10P30/00; H10P30/20; H10P30/222
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
65 words
A gate structure for a semiconductor transistor, comprising: a lower polysilicon region doped at a first concentration; an upper polysilicon region doped at a second concentration, said second concentration different than said first concentration; and a conductive barrier layer, disposed between said lower and said upper polysilicon regions; wherein said conductive barrier layer prevents diffusion of impurities between said lower and said upper polysilicon regions.
Claim 2
Dependent Claim
65 words
A gate structure for a semiconductor transistor, comprising: a lower polysilicon region doped at a first concentration; an upper polysilicon region doped at a second concentration, said second concentration different than said first concentration; and a conductive barrier layer, disposed between said lower and said upper polysilicon regions; wherein said conductive barrier layer prevents diffusion of impurities between said lower and said upper polysilicon regions.
Claim 3
Dependent Claim
17 words
The gate structure of claim 1 , wherein said second concentration is less than said first concentration.
Claim 4
Dependent Claim
18 words
The gate structure of claim 1 , further comprising a silicide layer disposed on said upper polysilicon region.
Claim 5
Dependent Claim
35 words
The gate structure of claim 3 , wherein said silicide layer is selected from the group of: cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), and combinations comprising at least one of the foregoing.
Claim 6
Dependent Claim
26 words
The gate structure of claim 1 , wherein at least one of said lower polysilicon region and said upper polysilicon region comprises silicon germanium carbon (SiGeC).
Claim 7
Dependent Claim
41 words
The gate structure of claim 1 , wherein said lower polysilicon region is doped at a concentration of about 1×10 21 atoms/cm 3 , and said upper polysilicon region is doped at a concentration of about 3×10 20 atoms/cm 3 .
Claim 8
Dependent Claim
55 words
The gate structure of claim 1 , wherein said conductive barrier layer is selected from the group of: tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN), aluminum titanium nitride (AlTiN), titanium silicide (TiSi), quantum conductive semi-insulating barriers, and combinations comprising at least one of the foregoing.
Claim 9
Dependent Claim
99 words
A metal oxide semiconductor (MOS) transistor device, comprising: a source diffusion region and a drain diffusion region; and a gate stack structure disposed upon a gate dielectric, said gate stack structure further comprising: a lower polysilicon region doped at a first dopant concentration; a conductive barrier layer, disposed on said lower polysilicon region; and an upper polysilicon region, disposed on said conductive barrier layer, said upper polysilicon region doped at a second concentration, said second concentration being different than said first concentration; wherein said conductive barrier layer prevents diffusion of impurities between said lower and said upper polysilicon regions.
Claim 10
Dependent Claim
99 words
A metal oxide semiconductor (MOS) transistor device, comprising: a source diffusion region and a drain diffusion region; and a gate stack structure disposed upon a gate dielectric, said gate stack structure further comprising: a lower polysilicon region doped at a first dopant concentration; a conductive barrier layer, disposed on said lower polysilicon region; and an upper polysilicon region, disposed on said conductive barrier layer, said upper polysilicon region doped at a second concentration, said second concentration being different than said first concentration; wherein said conductive barrier layer prevents diffusion of impurities between said lower and said upper polysilicon regions.
Claim 11
Dependent Claim
17 words
The transistor device of claim 8 , wherein said second concentration is less than said first concentration.
Claim 12
Dependent Claim
18 words
The transistor device of claim 8 , further comprising a silicide layer disposed on said upper polysilicon region.
Claim 13
Dependent Claim
35 words
The transistor device of claim 10 , wherein said silicide layer is selected from the group of: cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), and combinations comprising at least one of the foregoing.
Claim 14
Dependent Claim
26 words
The transistor device of claim 8 , wherein at least one of said lower polysilicon region and said upper polysilicon region comprises silicon germanium carbon (SiGeC).
Claim 15
Dependent Claim
41 words
The transistor device of claim 8 , wherein said lower polysilicon region is doped at a concentration of about 1×10 21 atoms/cm 3 , and said upper polysilicon region is doped at a concentration of about 3×10 20 atoms/cm 3 .
Claim 16
Dependent Claim
55 words
The transistor device of claim 8 , wherein said conductive barrier layer is selected from the group of: tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), tungsten silicon nitride (WSiN), tantalum silicon nitride (TaSiN), aluminum titanium nitride (AlTiN), titanium silicide (TiSi), quantum conductive semi-insulating barriers, and combinations comprising at least one of the foregoing.
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