US5885887A
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Method of making an igfet with selectively doped multilevel polysilicon gate
Assignee: GlobalFoundries Inc
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Filing: 1997-04-21
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Granted: 1999-03-23
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Expires: 2017-04-21
Abstract
Abstract A method of making an IGFET with a selectively doped multilevel polysilicon gate that includes upper and lower polysilicon gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a a lower polysilicon layer on the gate insulator, forming a first masking layer over the lower polysilicon layer, etching the lower polysilicon layer through openings in the first masking layer using the first masking layer as an etch mask for a portion of the lower polysilicon layer that forms the lower polysilicon gate level over the active region, removing the first masking layer, forming the upper polysilicon gate level on the lower polysilicon gate level after removing the first masking layer, introducing a dopant into the upper polysilicon gate level without introducing the dopant into the substrate, diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level, and forming a source and drain in the active region. Advantageously, the lower polysilicon gate level has both an accurately defined length to provide the desired channel length and a well-controlled doping concentration to provide the desired threshold voltage.
Inventors
- 👤 Frederick N. Hause
- 👤 Robert Dawson
- 👤 H. Jim Fulford Jr.
- 👤 Mark I. Gardner
- 👤 Mark W. Michael
- 👤 Bradley T. Moore
- 👤 Derick J. Wristers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:51
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01324; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0177; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
169 words
A method of making an IGFET with a selectively doped multilevel polysilicon gate, comprising the steps of: providing a semiconductor substrate with an active region; forming a gate insulator on the active region; forming a lower polysilicon layer on the gate insulator; forming a first masking layer over the lower polysilicon layer; etching the lower polysilicon layer through openings in the first masking layer using the first masking layer as an etch mask for a portion of the lower polysilicon layer that forms a lower polysilicon gate level over the active region; removing the first masking layer; forming an upper polysilicon gate level on the lower polysilicon gate level after removing the first masking layer, wherein the multilevel polysilicon gate includes the upper and lower polysilicon gate levels; introducing a dopant into the upper polysilicon gate level without introducing the dopant into the substrate; diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level; and forming a source and drain in the active region.
Claim 2
Independent Claim
169 words
A method of making an IGFET with a selectively doped multilevel polysilicon gate, comprising the steps of: providing a semiconductor substrate with an active region; forming a gate insulator on the active region; forming a lower polysilicon layer on the gate insulator; forming a first masking layer over the lower polysilicon layer; etching the lower polysilicon layer through openings in the first masking layer using the first masking layer as an etch mask for a portion of the lower polysilicon layer that forms a lower polysilicon gate level over the active region; removing the first masking layer; forming an upper polysilicon gate level on the lower polysilicon gate level after removing the first masking layer, wherein the multilevel polysilicon gate includes the upper and lower polysilicon gate levels; introducing a dopant into the upper polysilicon gate level without introducing the dopant into the substrate; diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level; and forming a source and drain in the active region.
Claim 3
Dependent Claim
50 words
The method of claim 1, including: depositing an insulating layer over the substrate and on the lower polysilicon gate level after removing the first masking layer; polishing the insulating layer until a top surface of the lower polysilicon gate level is exposed; and then forming the upper polysilicon gate level.
Claim 4
Dependent Claim
81 words
The method of claim 1, including: depositing a upper polysilicon layer over the substrate, wherein a portion of the upper polysilicon layer provides the upper polysilicon gate level; forming a second masking layer over the upper polysilicon layer after implanting the dopant into the upper polysilicon gate level; etching the upper polysilicon layer through openings in the second masking layer using the second masking layer as an etch mask for the upper polysilicon gate level; and removing the second masking layer.
Claim 5
Dependent Claim
27 words
The method of claim 3, including diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level before etching the upper polysilicon layer.
Claim 6
Dependent Claim
27 words
The method of claim 3, including diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level after etching the upper polysilicon layer.
Claim 7
Dependent Claim
33 words
The method of claim 1, wherein forming the source and drain includes implanting lightly doped source and drain regions into the active region using the lower polysilicon gate level as an implant mask.
Claim 8
Dependent Claim
32 words
The method of claim 1, wherein forming the source and drain includes implanting lightly doped source and drain regions into the active region using the first masking layer as an implant mask.
Claim 9
Dependent Claim
33 words
The method of claim 1, wherein forming the source and drain provides implanting lightly doped source and drain regions into the active region using the upper polysilicon gate level as an implant mask.
Claim 10
Dependent Claim
32 words
The method of claim 1, wherein diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level provides a majority of doping for the lower polysilicon gate level.
Claim 11
Dependent Claim
28 words
The method of claim 1, including diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level without diffusing the dopant into the substrate.
Claim 12
Dependent Claim
19 words
The method of claim 1, wherein the lower polysilicon gate level has a thickness of at most 1000 angstroms.
Claim 13
Dependent Claim
24 words
The method of claim 1, wherein the upper polysilicon gate level has a substantially greater thickness than that of the lower polysilicon gate level.
Claim 14
Dependent Claim
16 words
An integrated circuit chip, including an IGFET fabricated in accordance with the method of claim 1.
Claim 15
Dependent Claim
26 words
An electronic system including a microprocessor, a memory and a system bus, and further including an IGFET fabricated in accordance with the method of claim 1.
Claim 16
Independent Claim
259 words
A method of making an IGFET with a selectively doped multilevel polysilicon gate, comprising the steps of: providing a semiconductor substrate with an active region; forming a gate insulator on the active region; forming a lower polysilicon layer on the gate insulator; forming a first photoresist layer over the lower polysilicon layer; irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region; etching the lower polysilicon layer through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the lower polysilicon layer that forms a lower polysilicon gate level over the active region; removing the first photoresist layer; depositing an insulating layer over the substrate and on the lower polysilicon gate level after removing the first photoresist layer; polishing the insulating layer so that a top surface of the lower polysilicon gate level is exposed; forming an upper polysilicon layer on the lower polysilicon gate level and the insulating layer after polishing the insulating layer, wherein the upper polysilicon layer includes an upper polysilicon gate level on the lower polysilicon gate level, and the multilevel polysilicon gate includes the upper and lower polysilicon gate levels; implanting a dopant into the upper polysilicon gate level without implanting the dopant into the substrate; diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level without diffusing the dopant into the substrate; and forming a source and drain in the active region.
Claim 17
Independent Claim
259 words
A method of making an IGFET with a selectively doped multilevel polysilicon gate, comprising the steps of: providing a semiconductor substrate with an active region; forming a gate insulator on the active region; forming a lower polysilicon layer on the gate insulator; forming a first photoresist layer over the lower polysilicon layer; irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region; etching the lower polysilicon layer through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the lower polysilicon layer that forms a lower polysilicon gate level over the active region; removing the first photoresist layer; depositing an insulating layer over the substrate and on the lower polysilicon gate level after removing the first photoresist layer; polishing the insulating layer so that a top surface of the lower polysilicon gate level is exposed; forming an upper polysilicon layer on the lower polysilicon gate level and the insulating layer after polishing the insulating layer, wherein the upper polysilicon layer includes an upper polysilicon gate level on the lower polysilicon gate level, and the multilevel polysilicon gate includes the upper and lower polysilicon gate levels; implanting a dopant into the upper polysilicon gate level without implanting the dopant into the substrate; diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level without diffusing the dopant into the substrate; and forming a source and drain in the active region.
Claim 18
Dependent Claim
76 words
The method of claim 15, including: forming a second photoresist layer over the upper polysilicon layer; irradiating the second photoresist layer with a second image pattern and removing irradiated portions of the second photoresist layer to provide openings above the active region; etching the upper polysilicon layer through the openings in the second photoresist layer using the second photoresist layer as an etch mask for the upper polysilicon gate level; and removing the second photoresist layer.
Claim 19
Dependent Claim
39 words
The method of claim 16, wherein: the second polysilicon layer has a substantially greater thickness than that of the first polysilicon layer; and the second photoresist layer has a substantially greater thickness than that of the first photoresist layer.
Claim 20
Dependent Claim
15 words
The method of claim 17, wherein the first and second image patterns are essentially identical.
Claim 21
Dependent Claim
27 words
The method of claim 17, including diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level before etching the upper polysilicon layer.
Claim 22
Dependent Claim
27 words
The method of claim 17, including diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level after etching the upper polysilicon layer.
Claim 23
Dependent Claim
32 words
The method of claim 17, wherein diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level provides a majority of doping for the lower polysilicon gate level.
Claim 24
Dependent Claim
26 words
The method of claim 17, including forming the upper polysilicon layer on substantially aligned top surfaces of the lower polysilicon gate level and the insulating layer.
Claim 25
Dependent Claim
19 words
The method of claim 17, wherein the lower polysilicon gate level has a thickness of at most 1000 angstroms.
Claim 26
Dependent Claim
19 words
The method of claim 17, wherein the multilevel polysilicon gate consists of the upper and lower polysilicon gate levels.
Claim 27
Independent Claim
338 words
A method of making first and second IGFETs with selectively doped multilevel polysilicon gates, comprising the steps of: providing a semiconductor substrate with first and second active regions; forming a gate insulator on the active regions; depositing a lower polysilicon layer on the gate insulator; forming a first photoresist layer over the lower polysilicon layer; irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above portions of the active regions; etching the lower polysilicon layer through the openings in the first photoresist layer using the first photoresist layer as an etch mask for portions of the lower polysilicon layer that form a first lower polysilicon gate level over the first active region and a second lower polysilicon gate level over the second active region; removing the first photoresist layer; depositing an insulating layer over the substrate and on the first and second lower polysilicon gate levels after removing the first photoresist layer; polishing the insulating layer so that top surfaces of the first and second lower polysilicon gate levels are exposed; depositing an upper polysilicon layer on the first and second lower polysilicon gate levels and the insulating layer after polishing the insulating layer, wherein the upper polysilicon layer includes a first upper polysilicon gate level on the first lower polysilicon gate level and a second upper polysilicon gate level on the second lower polysilicon gate level, a first multilevel polysilicon gate includes the first upper and lower polysilicon gate levels, and a second multilevel polysilicon gate includes the second upper and lower polysilicon gate levels; implanting a first dopant into the first upper polysilicon gate level without implanting the first dopant into the substrate; diffusing the first dopant from the first upper polysilicon gate level into the first lower polysilicon gate level without diffusing the dopant into the substrate; forming a first source and first drain in the first active region; and forming a second source and second drain in the second active region.
Claim 28
Independent Claim
338 words
A method of making first and second IGFETs with selectively doped multilevel polysilicon gates, comprising the steps of: providing a semiconductor substrate with first and second active regions; forming a gate insulator on the active regions; depositing a lower polysilicon layer on the gate insulator; forming a first photoresist layer over the lower polysilicon layer; irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above portions of the active regions; etching the lower polysilicon layer through the openings in the first photoresist layer using the first photoresist layer as an etch mask for portions of the lower polysilicon layer that form a first lower polysilicon gate level over the first active region and a second lower polysilicon gate level over the second active region; removing the first photoresist layer; depositing an insulating layer over the substrate and on the first and second lower polysilicon gate levels after removing the first photoresist layer; polishing the insulating layer so that top surfaces of the first and second lower polysilicon gate levels are exposed; depositing an upper polysilicon layer on the first and second lower polysilicon gate levels and the insulating layer after polishing the insulating layer, wherein the upper polysilicon layer includes a first upper polysilicon gate level on the first lower polysilicon gate level and a second upper polysilicon gate level on the second lower polysilicon gate level, a first multilevel polysilicon gate includes the first upper and lower polysilicon gate levels, and a second multilevel polysilicon gate includes the second upper and lower polysilicon gate levels; implanting a first dopant into the first upper polysilicon gate level without implanting the first dopant into the substrate; diffusing the first dopant from the first upper polysilicon gate level into the first lower polysilicon gate level without diffusing the dopant into the substrate; forming a first source and first drain in the first active region; and forming a second source and second drain in the second active region.
Claim 29
Dependent Claim
34 words
The method of claim 25, wherein: the first and second active regions are of first conductivity type; and the first and second sources and drains and the first dopant are of second conductivity type.
Claim 30
Dependent Claim
54 words
The method of claim 26, including: simultaneously implanting the first dopant into the first and second upper polysilicon levels; and simultaneously diffusing the first dopant from the first upper polysilicon gate level into the first lower polysilicon gate level and from the second upper polysilicon gate level into the second lower polysilicon gate level.
Claim 31
Dependent Claim
43 words
The method of claim 25, wherein: the first active region and the second source and second drain are of first conductivity type; and the second active region and the first dopant and the first source and first drain are of second conductivity type.
Claim 32
Dependent Claim
92 words
The method of claim 28, including: implanting the first dopant into the first upper polysilicon gate level without implanting the first dopant into the second upper polysilicon gate-level; implanting a second dopant of first conductivity type into the second upper polysilicon gate level without implanting the second dopant into the first upper polysilicon gate level; and simultaneously diffusing the first dopant from the first upper polysilicon gate level into the lower polysilicon gate level and the second dopant from the second upper polysilicon gate level into the second lower polysilicon gate level.
Claim 33
Dependent Claim
86 words
The method of claim 25, including: forming a second photoresist layer over the upper polysilicon layer after implanting the first dopant; irradiating the second photoresist layer with the first image pattern and removing irradiated portions of the second photoresist layer to provide openings above portions of the active regions; etching the upper polysilicon layer through the openings in the second photoresist layer using the second photoresist layer as an etch mask for the first and second upper polysilicon gate levels; and removing the second photoresist layer.
Claim 34
Dependent Claim
36 words
The method of claim 25, wherein diffusing the first dopant from the first upper polysilicon gate level into the first lower polysilicon gate level provides a majority of doping for the first lower polysilicon gate level.
Claim 35
Dependent Claim
34 words
The method of claim 25, including forming the upper polysilicon layer on substantially aligned top planar surfaces of the first lower polysilicon gate level, the second lower polysilicon gate level and the insulating layer.
Claim 36
Dependent Claim
22 words
The method of claim 25, wherein the first and second lower polysilicon gate levels have a thickness of at most 1000 angstroms.
Claim 37
Dependent Claim
25 words
The method of claim 25, wherein the first and second lower polysilicon gate levels have a thickness in the range of 500 to 1000 angstroms.
Claim 38
Dependent Claim
30 words
The method of claim 25, wherein the first and second upper polysilicon gate levels have a substantially greater thickness than that of the first and second lower polysilicon gate levels.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-03-22 | 2002-09-21 | 2003-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-03-22 | 2006-09-21 | 2007-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-03-22 | 2010-09-21 | 2011-03-23 | $7700.00 | Window Closed / Lapsed |