Apparatus and method for generating output clock signal having controlled timing

Claim 2

A circuit for generating an output clock signal having controlled timing, comprising: a first delay circuit which receives an input clock signal in order to generate a first delayed input clock signal, in which the first delayed input clock signal is an input clock signal delayed by a period determined according to a first delay control signal inputted to the first delay circuit; a second delay circuit which receives the input clock signal in order to generate a second delayed input clock signal, in which the second delayed input clock signal is an input clock signal delayed by a period determined according to a second delay control signal inputted to the second delay circuit; a phase blending circuit which receives the first and second delayed input clock signals and blending the phases of the first and second delayed input clock signals in order to generate a phase blended clock signal; a phase detection circuit which receives a reference clock signal and the phase blended clock signal in order to generate a phase push signal in the case that a phase of the phase blended clock signal is ahead of that of the reference clock signal, and generate a phase pull signal in the case that the phase of the phase blended clock signal is behind that of the reference clock signal; and a delay control circuit which generates the first or second delay control signal in order to increase the delay when the phase push signal is received from the phase detection circuit and decrease the delay when the phase pull signal is received from the phase detection circuit.

Claim 3

The circuit according to claim 1 , wherein the first delay control signal and the second delay control signal is generated in alternation.

Claim 4

The circuit according to claim 1 , wherein the first delay control signal and the second delay control signal are not generated simultaneously.

Claim 5

The circuit according to claim 1 , further comprises an input buffer for generating the input clock signal by receiving and buffering the reference clock signal.

Claim 6

The circuit according to claim 1 , further comprises an output buffer for generating the output clock signal by receiving and buffering the phase blended clock signal, wherein instead of the phase blended clock signal, the output clock signal is provided to the phase detection circuit.

Claim 7

The circuit according to claim 5 , further comprises a dummy delay circuit for receiving the output clock signal to generate a feedback clock signal, in which the feedback clock signal is a delayed signal of the output clock signal by the delay in the input buffer, wherein instead of the reference clock signal, the input clock signal is provided to the phase detection circuit, and instead of the output clock signal, the feedback clock signal is provided to the phase detection circuit.

Claim 8

The circuit according to claim 5 , further comprises a dummy delay circuit which receives the output clock signal in order to generate a feedback clock signal, in which the feedback clock signal is an output clock signal delayed by a predetermined period, wherein instead of the output clock signal, the feedback clock signal is provided to the phase detection circuit.

Claim 9

The circuit according to claim 1 , wherein the phase blending circuit comprises, a first inverter for receiving and inverting the first delayed input clock signal; a second inverter for receiving and inverting the second delayed input clock signal; and a third inverter for inverting output signals from the first and second inverters, in which an input terminal of the third inverter is connected to output terminals of the first and second inverters, and an output signal from the third inverter is provided as the phase blended clock signal.

Claim 10

A circuit for generating an output clock signal having controlled timing, comprising: an input buffer for generating an input clock signal by receiving and buffering a reference clock signal; a first delay circuit which receives the input clock signal to generate a first delayed input clock signal, in which the first delayed input clock signal is an input clock signal delayed by a period determined according to a first delay control signal inputted to the first delayed circuit; a second delay circuit which receives the input clock signal to generate a second delayed input clock signal, in which the second delayed input clock signal is an input clock signal delayed by a period determined according to a second delay control signal inputted to the second delayed circuit; a phase blending circuit for receiving the first and second delayed input clock signals and blending phases of the first and second delayed input clock signals to generate a phase blended clock signal; an output buffer which receives and buffers the phase blended clock signal in order to generate the output clock signal; a phase detection circuit which receives the reference clock signal and the output clock signal in order to generate a phase push signal in the case that a phase of the output clock signal is ahead of that of the reference clock signal and to generate a phase pull signal in the case that the phase of the output clock signal is behind that of the reference clock signal; and a delay control circuit which generates the first or second delay control signal in order to increase the delay when the phase push signal is received from the phase detection circuit and decrease the delay when the phase pull signal is received from the phase detection circuit, in which the first delay control signal and the second delay control signal are not generated simultaneously.

Claim 11

A circuit for generating an output clock signal having controlled timing, comprising: an input buffer for generating an input clock signal by receiving and buffering a reference clock signal; a first delay circuit which receives the input clock signal to generate a first delayed input clock signal, in which the first delayed input clock signal is an input clock signal delayed by a period determined according to a first delay control signal inputted to the first delayed circuit; a second delay circuit which receives the input clock signal to generate a second delayed input clock signal, in which the second delayed input clock signal is an input clock signal delayed by a period determined according to a second delay control signal inputted to the second delayed circuit; a phase blending circuit for receiving the first and second delayed input clock signals and blending phases of the first and second delayed input clock signals to generate a phase blended clock signal; an output buffer which receives and buffers the phase blended clock signal in order to generate the output clock signal; a phase detection circuit which receives the reference clock signal and the output clock signal in order to generate a phase push signal in the case that a phase of the output clock signal is ahead of that of the reference clock signal and to generate a phase pull signal in the case that the phase of the output clock signal is behind that of the reference clock signal; and a delay control circuit which generates the first or second delay control signal in order to increase the delay when the phase push signal is received from the phase detection circuit and decrease the delay when the phase pull signal is received from the phase detection circuit, in which the first delay control signal and the second delay control signal are not generated simultaneously.

Claim 12

The circuit according to claim 9 , wherein the first and second control signals are generated in alternation.

Claim 13

The circuit according to claim 9 , circuit further comprises a dummy delay circuit for receiving the output clock signal to generate a feedback clock signal, in which the feedback clock signal is an output clock signal delayed by the delay in the input buffer, wherein instead of the reference clock signal, the input clock signal is provided to the phase detection circuit, and instead of the output clock signal, the feedback clock signal is provided to the phase detection circuit.

Claim 14

The circuit according to claim 9 , further comprise a dummy delay circuit which receives the output clock signal in order to generate a feedback clock signal, in which the feedback clock signal is an output clock signal delayed by the period in the input buffer, wherein the feedback clock signal is provided to the phase detection circuit, instead of the output clock signal.

Claim 15

The circuit according to claim 9 , wherein the phase blending circuit comprises, a first inverter for receiving and inverting the first delayed input clock signal; a second inverter for receiving and inverting the second delayed input clock signal; and a third inverter for inverting output signals from the first and second inverters, in which an input terminal of the third inverter is connected to output terminals of the first and second inverters, and an output signal of the third inverter is provided as the phase blending clock signal.

Claim 18

The method according to claim 14 , wherein the first delay control signal and the second delay control signal are not generated simultaneously and are generated in alternation.

Claim 19

The method according to claim 14 , the method further comprises a step of generating the input clock signal by receiving and buffering the reference clock signal.

Claim 20

The method according to claim 14 , further comprises a clock buffering step for generating the output clock signal by receiving and buffering the phase blended clock signal, wherein in the step of generating the phase push or pull signal, instead of the phase blended clock signal, the output clock signal is used.

Claim 21

The method according to claim 17 , further comprises a dummy clock receiving step for receiving the output clock signal to generate a feedback clock signal, in which the feedback clock signal is an output clock signal delayed by the period in the dummy clock receiving step, wherein in the step of generating the phase push or pull signal, instead of the reference clock signal, the input clock signal is used, and instead of the output clock signal, the feedback clock signal is used.

Claim 22

The method according to claim 17 , further comprises a dummy delay step for receiving the output clock signal to generate a feedback clock signal, in which the feedback clock signal is an output clock signal delayed by a predetermined period, wherein in the step of generating the phase push or pull signal, instead of the output clock signal, the feedback clock signal is used.