US6573771B2
Expired / Lapsed
US
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Clock synchronization circuit having improved jitter property
Assignee: SK Hynix Inc
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Filing: 2002-05-02
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Granted: 2003-06-03
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Expires: 2022-05-02
Abstract
Abstract A clock synchronization circuit. The clock synchronization circuit composed of a digital DLL outputs a clock signal delayed by a variable delay line and a clock signal delayed by an additional delay cell, mixes the two clock signals, and outputs an internal clock signal having a smaller delay than a delay time of a delay cell, thereby rapidly precisely synchronizing an external clock signal and the internal clock signal. In addition, a driving unit and a control unit for adjusting a duty cycle are provided to set up a ratio of 50%, thereby improving operation performance.
Inventors
- 👤 Seong-Hoon Lee
- 👤 Jong Tae Kwak
- 👤 Chang-Ki Kwon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:18
CPC Classifications
G; G11; G11C; G11C8/00; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/089; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
155 words
A clock synchronization circuit receiving an external clock signal, the clock synchronization comprising: a clock synchronization control means for outputting a normal delay clock signal by delaying the external clock signal for a predetermined time, and outputting an additional delay clock signal by delaying the normal delay clock signal; a phase mixing means for mixing phases of the normal delay clock signal and the additional delay clock signal from the clock synchronization control means, and outputting an internal clock signal; a control means for controlling the operation of the phase mixing means, and determining a phase of the internal clock signal; a shift register for controlling a delay time of the clock synchronization means; and a phase detecting means for comparing a phase of the external clock signal with a phase of the internal clock signal, and controlling the shift register to equalize the phases of the external clock signal and the internal clock signal.
Claim 2
Dependent Claim
155 words
A clock synchronization circuit receiving an external clock signal, the clock synchronization comprising: a clock synchronization control means for outputting a normal delay clock signal by delaying the external clock signal for a predetermined time, and outputting an additional delay clock signal by delaying the normal delay clock signal; a phase mixing means for mixing phases of the normal delay clock signal and the additional delay clock signal from the clock synchronization control means, and outputting an internal clock signal; a control means for controlling the operation of the phase mixing means, and determining a phase of the internal clock signal; a shift register for controlling a delay time of the clock synchronization means; and a phase detecting means for comparing a phase of the external clock signal with a phase of the internal clock signal, and controlling the shift register to equalize the phases of the external clock signal and the internal clock signal.
Claim 3
Dependent Claim
121 words
The circuit according to claim 1 , wherein the clock synchronization control means comprises: a plurality of select output means for selectively outputting the external clock signal according to a plurality of output signals from the shift register; a plurality of unit delay cells connected in series for delaying the external clock signal selectively outputted by the select output means; an output driving means having an input terminal connected to receive a power voltage and its other input terminal connected to receive the output signal from the last unit delay cell, and outputting the normal delay output signal; and an additional delay cell for delaying the normal delay output signal for a predetermined time, and outputting the additional delay clock signal.
Claim 4
Dependent Claim
86 words
The circuit according to claim 2 , wherein the unit delay cell comprises: a first delay device having a first input terminal connected to receive the output signal from the previous unit delay cell, and a second input terminal connected to receive the external clock signal selectively outputted by the corresponding select output means; and a second delay device having a first input terminal connected to receive the power voltage, and a second input terminal connected to receive the output signal from the first delay device.
Claim 5
Dependent Claim
83 words
The circuit according to claim 2 , wherein the additional delay cell comprises: a first additional delay device having a first input terminal connected to receive the power voltage, and a second input terminal connected to receive the normal delay clock signal; and a second additional delay device having a first input terminal connected to receive the power voltage and a second input terminal connected to receive the output signal from the first additional delay device, and outputting the additional delay clock signal.
Claim 6
Dependent Claim
29 words
The circuit according to claim 2 , wherein the additional delay cell has the same structure as the unit delay cell, and thus has the same unit delay time.
Claim 7
Dependent Claim
85 words
The circuit according to claim 1 , wherein the phase mixing means comprises: a plurality of normal driving means for selectively driving the normal delay clock signal according to the control signal from the control means; a plurality of additional driving means for selectively driving the additional delay clock signal according to the control signal from the control means; and a clock mixing means for mixing the signals driven by the normal driving means and the additional driving means, and outputting the internal clock signal.
Claim 8
Dependent Claim
93 words
The circuit according to claim 6 , receiving a power voltage and a ground voltage, wherein the normal driving means comprises: a first PMOS transistor and a first NMOS transistor being connected in series between the power voltage and ground voltage, and having their gates connected to receive the normal delay clock signal; and a second PMOS transistor and a second NMOS transistor having their gates connected to receive the corresponding control signal from the control means, commonly-connected drains of the second PMOS transistor and the second NMOS transistor composing an output terminal.
Claim 9
Dependent Claim
93 words
The circuit according to claim 6 , receiving a power voltage and a ground voltage, wherein the additional driving means comprises: a first PMOS transistor and a first NMOS transistor being connected in series between the power voltage and ground voltage, and having their gates connected to receive the additional delay clock signal; and a second PMOS transistor and a second NMOS transistor having their gates connected to receive the corresponding control signal from the control means, commonly-connected drains of the second PMOS transistor and the second NMOS transistor composing an output terminal.
Claim 10
Dependent Claim
57 words
The circuit according to claim 1 , further comprising: a duty cycle driving means for driving the internal clock signal, and adjusting a duty cycle; and a control means for detecting a duty cycle of the output signal from the duty cycle driving means, and controlling the duty cycle driving means to have a previously-set duty cycle.
References Cited (Backward Citations)
US5875219A
Cited
US6483359B2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-06-02 | 2006-12-02 | 2007-06-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-06-02 | 2010-12-02 | 2011-06-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-06-02 | 2014-12-02 | 2015-06-03 | $7700.00 | Window Closed / Lapsed |