Patent US6674679B1 successfully refreshed from Google Patents.
US6674679B1
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Adjustable current mode differential amplifier for multiple bias point sensing of MRAM having equi-potential isolation
Assignee: Samsung Electronics Co Ltd
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Filing: 2002-10-01
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Granted: 2004-01-06
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Expires: 2022-10-01
Abstract
Abstract An adjustable current mode differential sense amplifier is disposed to be in communication with a selected memory cell and a reference cell having a predetermined value. The amplifier is able to sense current and voltage changes associated with the selected memory cell and compare them to current and voltage changes associated with the reference cell. The operating point of the sensing amplifier may be changed by modifying threshold voltages related to the back gate bias applied to selected transistors in the amplifier. This adjusting capability enables currents or voltages of the sense amplifier to be set when a first bias voltage is applied to a selected memory cell in order to maximize the sensitivity of the amplifier. When a second bias voltage is applied to the memory and reference cells in order to determine the memory cell value, the amplifier is able to sense slight changes in the currents or voltages associated with the selected memory cell and the reference cell and compare them to determine the state of the memory cell. This increased sensitivity enables the amplifier to have a substantially increased dynamic range without introducing components that might adversely affect the memory circuitry parameters. The memory cell array being sensed has equi-potential isolation for all unselected memory cells, thereby minimizing sneak currents through the unselected memory cells.
Inventors
- 👤 Frederick A. Perner
- 👤 Anthony P. Holden
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:49
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/06; G11C7/062; G11C11/00; G11C11/02; G11C11/16; G11C11/165; G11C11/1673; G11C13/00; G11C13/0002; G11C13/0021; G11C13/0033; G11C13/004; G11C2013/0054; G11C2207/00; G11C2207/06; G11C2207/063; G11C2213/00; G11C2213/70; G11C2213/77
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
246 words
A sensing circuit for determining the logic state of a selected memory cell in a Resistive memory array, the logic state of the memory cell being determined relative to a reference cell having a pre-selected logic state, comprising: (a) a memory cell sensing circuit adapted to determine a first memory cell voltage associated with the memory cell when a first bias voltage is impressed on the memory cell and to determine a second memory cell voltage associated with the memory cell when a second bias voltage is impressed on the memory cell, (b) a reference cell sensing circuit adapted to determine a first reference cell voltage associated with the reference cell when the first bias voltage is impressed on the reference cell and to determine a second reference cell voltage associated with the reference cell when the second bias voltage is impressed on the reference cell, (c) an equi-potential isolation circuit for applying a substantially equal voltage to both sides of each unselected memory cell; (d) an adjusting circuit for modifying at least one of (i) the first memory cell voltage and (ii) the first reference cell voltage to make the first memory cell voltage approximately equal to the first reference cell voltage at the first bias voltage, and (e) a state determining circuit for determining the difference between the second memory cell voltage and the second reference cell voltage in order to determine the logic state of the memory cell at the second bias voltage.
Claim 2
Dependent Claim
246 words
A sensing circuit for determining the logic state of a selected memory cell in a Resistive memory array, the logic state of the memory cell being determined relative to a reference cell having a pre-selected logic state, comprising: (a) a memory cell sensing circuit adapted to determine a first memory cell voltage associated with the memory cell when a first bias voltage is impressed on the memory cell and to determine a second memory cell voltage associated with the memory cell when a second bias voltage is impressed on the memory cell, (b) a reference cell sensing circuit adapted to determine a first reference cell voltage associated with the reference cell when the first bias voltage is impressed on the reference cell and to determine a second reference cell voltage associated with the reference cell when the second bias voltage is impressed on the reference cell, (c) an equi-potential isolation circuit for applying a substantially equal voltage to both sides of each unselected memory cell; (d) an adjusting circuit for modifying at least one of (i) the first memory cell voltage and (ii) the first reference cell voltage to make the first memory cell voltage approximately equal to the first reference cell voltage at the first bias voltage, and (e) a state determining circuit for determining the difference between the second memory cell voltage and the second reference cell voltage in order to determine the logic state of the memory cell at the second bias voltage.
Claim 3
Dependent Claim
34 words
The sensing circuit of claim 1 , wherein the equi-potential isolation circuit comprises a first pass transistor connected to the selected memory cell and a second pass transistor connected to the unselected memory cells.
Claim 4
Dependent Claim
27 words
The sensing circuit of claim 2 , wherein the first and second pass transistors are each connected to an op-amp to constitute a direct injection charge amplifier.
Claim 5
Dependent Claim
59 words
The sensing circuit of claim 3 , and further comprising a comparator circuit in communication with a memory cell node and a reference cell node for generating an output voltage in response to the difference between the second memory cell voltage and the second reference cell voltage, said difference being indicative of the logic state of the memory cell.
Claim 6
Dependent Claim
43 words
The sensing circuit of claim 1 wherein the state determining circuit comprises a device for comparing (i) the difference between the memory cell voltage and the reference cell voltage to (ii) a threshold value to determine the logic state of the memory cell.
Claim 7
Dependent Claim
45 words
The sensing circuit of claim 1 wherein the state determining circuit comprises a device for determining the positive or negative nature of the difference between the memory cell voltage and the reference cell voltage in order to determine the logic state of the memory cell.
Claim 8
Dependent Claim
38 words
The sensing circuit of claim 1 wherein the memory cell sensing circuit comprises a sensing transistor and the reference cell sensing circuit comprises a reference transistor having its gate in common with the gate of the sensing transistor.
Claim 9
Dependent Claim
56 words
The sensing circuit of claim 7 wherein the adjusting circuit comprises a voltage adjusting device connected to a back gate of the sensing transistor and/or the reference transistor to selectively modify the voltage on the back gate to a balance point where the first reference cell voltage is approximately equal to the first memory cell voltage.
Claim 10
Dependent Claim
30 words
The sensing circuit of claim 8 and further comprising an electrical storage device associated with the back gate to maintain the voltage on the back gate at the balance point.
Claim 11
Dependent Claim
30 words
The sensing circuit of claim 8 wherein the voltage adjusting device comprises a variable voltage generator and a device for selectively connecting the variable voltage generator to the back gate.
Claim 12
Dependent Claim
63 words
The sensing circuit of claim 10 further comprising a comparator in communication with the variable voltage generator and in communication with a memory cell node and a reference cell node for determining the difference between the first memory cell voltage and the first reference cell voltage and for selectively connecting the variable voltage generator to the back gate in response to said difference.
Claim 13
Dependent Claim
219 words
A sensing circuit for determining the logic state of a selected memory cell in a resistive memory array, using a reference cell previously set to a known logic state, comprising: (a) a first bias voltage source for applying a first bias voltage to the memory cell and the reference cell; (b) a first sensing device for sensing a first memory cell voltage associated with the memory cell and a first reference cell voltage associated with the reference cell, both at the first bias voltage; (c) an equi-potential isolation circuit for applying a substantially equal voltage to both sides of each unselected memory cell; (d) an adjusting device for modifying the first memory cell voltage and/or first reference cell voltage so that the first reference cell voltage is approximately equal to the first memory cell voltage; (e) a second bias voltage source for applying a second bias voltage to the memory cell and the reference cell; (f) a second sensing device for sensing a second memory cell voltage associated with the memory cell and a second reference cell voltage associated with the reference cell, both at the second bias voltage; and (g) a comparing circuit for comparing the difference between the second memory cell voltage and the second reference cell voltage to determine the logic state of the memory cell.
Claim 14
Dependent Claim
219 words
A sensing circuit for determining the logic state of a selected memory cell in a resistive memory array, using a reference cell previously set to a known logic state, comprising: (a) a first bias voltage source for applying a first bias voltage to the memory cell and the reference cell; (b) a first sensing device for sensing a first memory cell voltage associated with the memory cell and a first reference cell voltage associated with the reference cell, both at the first bias voltage; (c) an equi-potential isolation circuit for applying a substantially equal voltage to both sides of each unselected memory cell; (d) an adjusting device for modifying the first memory cell voltage and/or first reference cell voltage so that the first reference cell voltage is approximately equal to the first memory cell voltage; (e) a second bias voltage source for applying a second bias voltage to the memory cell and the reference cell; (f) a second sensing device for sensing a second memory cell voltage associated with the memory cell and a second reference cell voltage associated with the reference cell, both at the second bias voltage; and (g) a comparing circuit for comparing the difference between the second memory cell voltage and the second reference cell voltage to determine the logic state of the memory cell.
Claim 15
Dependent Claim
34 words
The sensing circuit of claim 12 , wherein the equi-potential isolation circuit comprises a first pass transistor connected to the selected memory cell and a second pass transistor connected to the unselected memory cells.
Claim 16
Dependent Claim
27 words
The sensing circuit of claim 13 , wherein the first and second pass transistors are each connected to an op-amp to constitute a direct injection charge amplifier.
Claim 17
Independent Claim
189 words
A method of determining the logic state of a memory cell in a resistive memory array relative to a reference cell having a pre-selected logic state, comprising: (a) sensing a first memory cell voltage associated with the memory cell when a first bias voltage is impressed on the memory cell and sensing a second memory cell voltage associated with the memory cell when a second bias voltage is impressed on the memory cell; (b) sensing a first reference cell voltage associated with the reference cell when the first bias voltage is impressed on the reference cell and sensing a second reference cell voltage associated with the reference cell when the second bias voltage is impressed on the reference cell; (c) applying an equi-potential isolation voltage to both sides of each unselected memory cell; (d) modifying the first memory cell voltage and/or the first reference cell voltage to make the first memory cell voltage approximately equal to the first reference cell voltage; and (e) determining the difference between the second memory cell voltage and the second reference cell voltage in order to determine the logic state of the memory cell.
Claim 18
Independent Claim
189 words
A method of determining the logic state of a memory cell in a resistive memory array relative to a reference cell having a pre-selected logic state, comprising: (a) sensing a first memory cell voltage associated with the memory cell when a first bias voltage is impressed on the memory cell and sensing a second memory cell voltage associated with the memory cell when a second bias voltage is impressed on the memory cell; (b) sensing a first reference cell voltage associated with the reference cell when the first bias voltage is impressed on the reference cell and sensing a second reference cell voltage associated with the reference cell when the second bias voltage is impressed on the reference cell; (c) applying an equi-potential isolation voltage to both sides of each unselected memory cell; (d) modifying the first memory cell voltage and/or the first reference cell voltage to make the first memory cell voltage approximately equal to the first reference cell voltage; and (e) determining the difference between the second memory cell voltage and the second reference cell voltage in order to determine the logic state of the memory cell.
Claim 19
Dependent Claim
38 words
The method of claim 15 wherein the determining step involves comparing the difference between the second memory cell voltage and the second reference cell voltage to a threshold value to determine the logic state of the memory cell.
Claim 20
Dependent Claim
40 words
The method of claim 15 wherein the determining step involves determining the positive or negative nature of the difference between the second memory cell voltage and the second reference cell voltage to determine the logic state of the memory cell.
Claim 21
Dependent Claim
40 words
The method of claim 15 wherein applying the equi-potential isolation voltage comprises connecting a direct injection charge amplifier to the unselected memory cells and applying a common voltage to the direct injection charge amplifier and to the unselected memory cells.
Claim 22
Dependent Claim
40 words
The method of claim 15 , wherein a sensing transistor is used to sense the memory cell and a reference transistor having its gate in common with the gate of the sensing transistor is used to sense the reference cell.
Claim 23
Dependent Claim
55 words
The method of claim 19 , wherein the modifying step comprises adjusting the voltage applied to the back gate of the sensing transistor and/or the reference transistor to selectively modify the voltage on the back gate to a balance point where the first reference cell voltage is approximately equal to the first memory cell voltage.
Claim 24
Dependent Claim
24 words
The method of claim 20 , wherein the voltage on the back gate is maintained at the balance point by an electrical storage device.
Claim 25
Dependent Claim
26 words
The method of claim 20 , wherein the voltage is adjusted on the back gate by selectively applying a variable voltage generator to the back gate.
Claim 26
Independent Claim
184 words
A method for determining the logic state of a selected memory cell in a resistive memory array, using a reference cell previously set to a known logic state, comprising: (a) applying a first bias voltage to the selected memory cell and the reference cell; (b) measuring a first memory cell voltage associated with the selected memory cell and a first reference cell voltage associated with the reference cell, both at the first bias voltage; (c) adjusting the first memory cell voltage and/or first reference cell voltage so that the first reference cell voltage is approximately equal to the first memory cell voltage; (d) applying a second bias voltage to the memory cell and the reference cell; (e) measuring a second memory cell voltage associated with the memory cell and a second reference cell voltage associated with the reference cell, both at the second bias voltage; (f) applying an equi-potential isolation voltage to both sides of each unselected memory cell; (g) comparing the difference between the second memory cell voltage and the second reference cell voltage to determine the logic state of the memory cell.
Claim 27
Independent Claim
184 words
A method for determining the logic state of a selected memory cell in a resistive memory array, using a reference cell previously set to a known logic state, comprising: (a) applying a first bias voltage to the selected memory cell and the reference cell; (b) measuring a first memory cell voltage associated with the selected memory cell and a first reference cell voltage associated with the reference cell, both at the first bias voltage; (c) adjusting the first memory cell voltage and/or first reference cell voltage so that the first reference cell voltage is approximately equal to the first memory cell voltage; (d) applying a second bias voltage to the memory cell and the reference cell; (e) measuring a second memory cell voltage associated with the memory cell and a second reference cell voltage associated with the reference cell, both at the second bias voltage; (f) applying an equi-potential isolation voltage to both sides of each unselected memory cell; (g) comparing the difference between the second memory cell voltage and the second reference cell voltage to determine the logic state of the memory cell.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2007-01-05 | 2007-07-07 | 2008-01-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2011-01-05 | 2011-07-07 | 2012-01-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2015-01-05 | 2015-07-07 | 2016-01-06 | $7700.00 | Window Closed / Lapsed |