Resistive cross point memory arrays having a charge injection differential sense amplifier

Claim 2

An information storage device, comprising: a resistive cross point memory cell array; a plurality of word lines; a plurality of bit lines, wherein a group of memory cells are connected to a common word line and each memory cell in the group is connected to a single bit line; and a differential sensing amplifier, coupled to the memory cell array, comprising: first and second input nodes, the first input node selectively coupled to one of the plurality of bit lines connected to a reference cell within the cell array and the second input node selectively coupled to a sense cell within the group of memory cells common to a given word line; a first preamplifier coupled to the first input node; a second preamplifier coupled to the second input node; and a charge injection amplifier, coupled to an output from the first preamplifier and an output from the second preamplifier, operable to determine a resistive state of the sense cell as compared to a resistive state of the reference cell during a read operation.

Claim 3

The invention according to claim 1 wherein the charge injection amplifier determines the resistive state of the sense cell by comparing current flowing through the sense cell with current flowing through one or more reference cells.

Claim 4

The invention according to claim 1 further comprising multiple read circuits each coupled to one or more associated groups of memory cells by a respective bit line and operable to sense current flow through a memory cell of the associated groups.

Claim 5

The invention according to claim 1 further comprising multiple comparator circuits each coupled to an associated read circuit and operable to convert an analog differential sense voltage to a digital output read signal.

Claim 6

The invention according to claim 1 further comprising an equipotential generator coupled to the word lines and the bit lines and operable to set voltage levels in the restive cross point memory cell array on selected word lines and bit lines to substantially prevent parasitic currents from flowing through unselected memory cells.

Claim 7

The invention according to claim 5 wherein each cell includes an isolation diode to connect the cell to the bit line, the voltage source is operable to set an input node of the common isolation diode of each group of memory cells with feedback from unselected word lines.

Claim 8

The invention according to claim 1 wherein each memory cell comprises a magnetic random access memory element.

Claim 9

The invention according to claim 1 wherein the charge injection amplifier comprises: a current mirror having a first input coupled to the first preamplifier for receiving a reference current based on the reference current from the reference cell and a second input coupled to the second preamplifier for receiving a sense current based on the sense current from the sense cell; a precharge circuit, coupled to the second preamplifier, the precharge circuit being charged to a selected potential prior to a read operation; a comparator amplifier, coupled to the precharge circuit and a reference voltage, wherein during a read operation, and as modified by the potential on the precharge circuit, if the sense current from the second preamplifier is greater than the reference current from the first preamplifier the comparator provides a first output or if the reference current is greater than the sense current, the comparator provides a second output as modified by the precharge circuit.

Claim 10

An information storage device, comprising: a resistive cross point memory cell array; a plurality of word lines; a plurality of bit lines, wherein the memory cells are arranged into multiple groups of two or more memory cells, each of the memory cells of each group being connected between a respective bit line and a common isolation diode coupled to a common word line; and a differential sensing amplifier, coupled to the memory cell array, comprising: first and second input nodes, the first input node selectively coupled to one of the plurality of bit lines connected to a reference cell within the cell array and the second input node selectively coupled to a sense cell within the memory array; a first preamplifier coupled to the first input node; a second preamplifier coupled to the second input node; and a charge injection amplifier, coupled to an output from the first preamplifier and an output from the second preamplifier, and being operable to determine a resistive state of the sense cell as compared to a resistive state of the reference cell during a read operation.

Claim 11

An information storage device, comprising: a resistive cross point memory cell array; a plurality of word lines; a plurality of bit lines, wherein the memory cells are arranged into multiple groups of two or more memory cells, each of the memory cells of each group being connected between a respective bit line and a common isolation diode coupled to a common word line; and a differential sensing amplifier, coupled to the memory cell array, comprising: first and second input nodes, the first input node selectively coupled to one of the plurality of bit lines connected to a reference cell within the cell array and the second input node selectively coupled to a sense cell within the memory array; a first preamplifier coupled to the first input node; a second preamplifier coupled to the second input node; and a charge injection amplifier, coupled to an output from the first preamplifier and an output from the second preamplifier, and being operable to determine a resistive state of the sense cell as compared to a resistive state of the reference cell during a read operation.

Claim 12

The invention according to claim 9 wherein the charge injection amplifier determines the resistive state of the sense cell by comparing current flowing through the sense cell with current flowing through one or more reference cells.

Claim 13

The invention according to claim 9 further comprising multiple read circuits each coupled to one or more associated groups of memory cells by a respective bit line and operable to sense current flow through a memory cell of the associated groups.

Claim 14

The invention according to claim 9 further comprising multiple comparator circuits each coupled to an associated read circuit and operable to convert an analog differential sense voltage to a digital output read signal.

Claim 15

The invention according to claim 9 further comprising a voltage source coupled to the word lines and the bit lines and operable to set voltage levels in the restive cross point memory cell array on selected word lines and bit lines to substantially prevent parasitic currents from flowing through unselected memory cells.

Claim 16

The invention according to claim 13 wherein the voltage source is operable to set an input node of the common isolation diode of each group of memory cells with feedback from unselected word lines.

Claim 17

The invention according to claim 9 wherein each memory cell comprises a magnetic random access memory element.

Claim 18

The invention according to claim 9 wherein the charge injection amplifier comprises: a current mirror having a first input coupled to the first preamplifier for receiving a reference current based on the reference current from the reference cell and a second input coupled to the second preamplifier for receiving a sense current based on the sense current from the sense cells; a precharge circuit, coupled to the second preamplifier, the precharge circuit being charged to a selected potential prior to a read operation; a comparator amplifier, coupled to the precharge circuit and a reference voltage, wherein during a read operation, and as modified by the potential on the precharge circuit, when the sense current from the second preamplifier is greater than the reference current from the first preamplifier the comparator provides a first output, when the reference current is greater than the sense current, the comparator provides a second output.

Claim 19

A differential amplifier using charge injection for determining a first or second resistive state of a selected circuit based on a comparison of a resistive state of a reference circuit, comprising: a first preamplifier coupled to the reference circuit; a second preamplifier, coupled to the selected circuit; a current mirror having a first input coupled to the first preamplifier for receiving a reference current based on the reference current from the reference circuit and a second input coupled to the second preamplifier for receiving a sense current based on the sense current from the selected circuit; a precharge circuit, coupled to the second preamplifier, the precharge circuit being charged to a selected potential prior to a read operation; and a comparator amplifier, coupled to the precharge circuit, wherein during a read operation, and as influenced by the potential on the precharge circuit, if the sense current from the second preamplifier is greater than the reference current from the first preamplifier the comparator provides a first output representing the first resistive state or if the reference current is greater than the sense current, the comparator provides a second output representing the second resistive state.

Claim 20

A differential amplifier using charge injection for determining a first or second resistive state of a selected circuit based on a comparison of a resistive state of a reference circuit, comprising: a first preamplifier coupled to the reference circuit; a second preamplifier, coupled to the selected circuit; a current mirror having a first input coupled to the first preamplifier for receiving a reference current based on the reference current from the reference circuit and a second input coupled to the second preamplifier for receiving a sense current based on the sense current from the selected circuit; a precharge circuit, coupled to the second preamplifier, the precharge circuit being charged to a selected potential prior to a read operation; and a comparator amplifier, coupled to the precharge circuit, wherein during a read operation, and as influenced by the potential on the precharge circuit, if the sense current from the second preamplifier is greater than the reference current from the first preamplifier the comparator provides a first output representing the first resistive state or if the reference current is greater than the sense current, the comparator provides a second output representing the second resistive state.

Claim 21

The invention according to claim 17 wherein the selected circuit includes a resistive memory sense cell and the reference circuit includes a resistive memory reference cell.

Claim 22

An information storage device, having a memory cell array with a plurality of sense cells and reference cells, each sense cell and reference cell having multiple states, a plurality of word lines, a plurality of bit lines and a differential sense amplifier, coupled to the memory cell array, the differential sense amplifier comprising: (a) first and second input nodes, the first input node being selectively coupled to a sense bit line connected to a selected sense cell within the array and the second input node being selectively coupled to a reference bit line connected to a selected reference cell within the array; (b) a first preamplifier coupled to the first input node and having an output providing a first current representative of a state of the selected sense cell; (c) a second preamplifier coupled to the second input node and having an output providing a second current representative of a state of the selected reference cell; and (d) a charge injection amplifier, coupled to the output of the first preamplifier and the output of the second preamplifier, and being operable to sense the difference between the first and second currents to determine the state of the selected sense cell.

Claim 23

An information storage device, having a memory cell array with a plurality of sense cells and reference cells, each sense cell and reference cell having multiple states, a plurality of word lines, a plurality of bit lines and a differential sense amplifier, coupled to the memory cell array, the differential sense amplifier comprising: (a) first and second input nodes, the first input node being selectively coupled to a sense bit line connected to a selected sense cell within the array and the second input node being selectively coupled to a reference bit line connected to a selected reference cell within the array; (b) a first preamplifier coupled to the first input node and having an output providing a first current representative of a state of the selected sense cell; (c) a second preamplifier coupled to the second input node and having an output providing a second current representative of a state of the selected reference cell; and (d) a charge injection amplifier, coupled to the output of the first preamplifier and the output of the second preamplifier, and being operable to sense the difference between the first and second currents to determine the state of the selected sense cell.

Claim 24

The information storage device according to claim 19 wherein the first preamplifier includes a mirror circuit for generating a first mirror current substantially identical to a current flowing through the selected sense cell, and the second preamplifier includes a second mirror circuit for generating a second mirror current substantially identical to a current flowing through the selected reference cell.

Claim 25

The information storage device according to claim 20 , wherein the charge injection amplifier includes a difference circuit operable for sensing the difference between the first and second mirror currents to determine the state of the selected sense cell.

Claim 26

The information storage device according to claim 21 , wherein the difference circuit comprises a subtracting circuit for subtracting the first and second mirror currents to generate a difference current, and a capacitor connected to the subtracting circuit for being charged or discharged by the difference current, depending on the magnitude of the difference current.

Claim 27

The information storage device according to claim 22 , wherein the difference circuit further comprises a comparator having an output representative of whether the capacitor is being charged or discharged.

Claim 30

The method according to claim 24 wherein the sensing step comprises determining the difference between the first current and the second current using a charge injection amplifier.

Claim 33

The method according to claim 26 , further comprising the step of connecting the difference current to a partially charged capacitor to charge or discharge the capacitor, depending on the magnitude of the difference current.

Claim 34

The method according to claim 27 , wherein the output signal is representative of whether the capacitor is being charged or discharged.