Dynamic wave-pipelined interface apparatus and methods therefor

Claim 2

An interface apparatus comprising: a plurality of delay devices, each device being operable for receiving a corresponding data signal, each delay device having a preselectable delay time, and outputting said data signal after preselected delay time; and circuitry coupled to said plurality of delay devices operable for setting each preselectedable delay time, each preselected delay being set in response to an arrival time associated with each data signal, wherein said circuitry operable for setting each preselectable delay comprises: data compare logic operable for receiving a predetermined subset of said data signals, an outputting a first predetermined output signal value when said subset of data signals comprises a first predetermined set of values, and outputting a second predetermined output signal value when said subset of data signals has a second predetermined set of values, wherein said subset of data signals assumes one of said first and second predetermined sets of values in response to said associated arrival times; and circuitry operable for modifying said preselected delay times in response to said first and second predetermined output signal values.

Claim 3

An interface apparatus comprising: a plurality of delay devices, each device being operable for receiving a corresponding data signal, each delay device having a preselectable delay time, and outputting said data signal after preselected delay time; and circuitry coupled to said plurality of delay devices operable for setting each preselectedable delay time, each preselected delay being set in response to an arrival time associated with each data signal, wherein said circuitry operable for setting each preselectable delay comprises: data compare logic operable for receiving a predetermined subset of said data signals, an outputting a first predetermined output signal value when said subset of data signals comprises a first predetermined set of values, an outputting a second predetermined output signal value when said subset of data signals has a second predetermined set of values, wherein said subset of data signals assumes one of said first and second predetermined sets of values in response to said associated arrival times; and circuitry operable for modifying said preselected delay times in response to said first and second predetermined output signal values, wherein said first predetermined set of values comprises a set of values wherein each value is the same, and said second predetermined set of values comprises a set of values wherein a first member and second member are different values.

Claim 4

An interface apparatus comprising: a plurality of delay devices, each device being operable for receiving a corresponding data signal, each delay device having a preselectable delay time, and outputting said data signal after preselected delay time; and circuitry coupled to said plurality of delay devices operable for setting each preselectedable delay time, each preselected delay being set in response to an arrival time associated with each data signal, wherein said circuitry operable for setting each preselectable delay comprises: data compare logic operable for receiving a predetermined subset of said data signals, an outputting a first predetermined output signal value when said subset of data signals comprises a first predetermined set of values, an outputting a second predetermined output signal value when said subset of data signals has a second predetermined set of values, wherein said subset of data signals assumes one of said first and second predetermined sets of values in response to said associated arrival times; and circuitry operable for modifying said preselected delay times in response to said first and second predetermined output signal values, wherein said first predetermined set of values comprises a set of values wherein each value is the same, and said second predetermined set of values comprises a set of values wherein a first member and second member are different values.

Claim 5

The interface apparatus of claim 1 wherein said circuitry operable for modifying said preselected delay times comprises: a state machine operable for modifying said preselected delay times in response to said first and second output signal values.

Claim 6

The interface apparatus of claim 3 wherein said circuitry operable for modifying said preselected delay times further comprises: a counter operable for receiving a direction signal from said state machine, said counter operable for outputting a count signal for determining a number of delay time increments for modifying said preselected delay times, wherein said delay time increment has a predetermined value.

Claim 7

The interface apparatus of claim 4 wherein said circuitry operable for modifying said preselected delay times further comprises delay control circuitry operable for receiving said count signal, and outputting a control signal to each of said plurality of delay devices, wherein said control signal is operable for modifying said preselected delay times.

Claim 8

An interface apparatus comprising: a plurality of delay devices, each device being operable for receiving a corresponding data signal, each delay device having a preselectable delay time, and outputting said data signal after preselected delay time; and circuitry coupled to said plurality of delay devices operable for setting each preselectedable delay time, each preselected delay being set in response to an arrival time associated with each data signal, wherein said circuitry operable for setting each preselectable delay comprises: data compare logic operable for receiving a predetermined subset of said data signals, an outputting a first predetermined output signal value when said subset of data signals comprises a first predetermined set of values, an outputting a second predetermined output signal value when said subset of data signals has a second predetermined set of values, wherein said circuitry for modifying said preselected delay times in response to said first and second predetermined signals comprises: a storage device having an input coupled to said compare logic, the logic state of said storage device being operable for setting in response to said first predetermined signal and resetting in response to said second predetermined signal; a counter coupled to said storage device operable for resetting said storage device after an elapse of a predetermined count; and circuitry operable for receiving said logic state of said storage device and modifying said preselected delay times in response to said logic state.

Claim 9

An interface apparatus comprising: a plurality of delay devices, each device being operable for receiving a corresponding data signal, each delay device having a preselectable delay time, and outputting said data signal after preselected delay time; and circuitry coupled to said plurality of delay devices operable for setting each preselectedable delay time, each preselected delay being set in response to an arrival time associated with each data signal, wherein said circuitry operable for setting each preselectable delay comprises: data compare logic operable for receiving a predetermined subset of said data signals, an outputting a first predetermined output signal value when said subset of data signals comprises a first predetermined set of values, an outputting a second predetermined output signal value when said subset of data signals has a second predetermined set of values, wherein said circuitry for modifying said preselected delay times in response to said first and second predetermined signals comprises: a storage device having an input coupled to said compare logic, the logic state of said storage device being operable for setting in response to said first predetermined signal and resetting in response to said second predetermined signal; a counter coupled to said storage device operable for resetting said storage device after an elapse of a predetermined count; and circuitry operable for receiving said logic state of said storage device and modifying said preselected delay times in response to said logic state.

Claim 10

A data processing system including an interface comprising: a central processing unit (CPU); a receiving device coupled to said CPU operable for receiving at least one data signal from said CPU, said receiving device including a data receive unit comprising: a plurality of delay devices, each device being operable for receiving a corresponding data signal, each delay device having a preselectable delay time, and outputting said data signal after said preselected delay time; and circuitry coupled to said plurality of delay devices operable for setting each preselectable delay time, each preselected delay time being set in response to an arrival time associated with each data signal, wherein said circuitry operable for setting each preselectable delay time comprises: data compare logic operable for receiving a predetermined subset of said data signals, and outputting a first predetermined output signal value when said subset of data signals comprises a first predetermined set of values, and outputting a second predetermined output signal value when said subset of data signals has a second predetermined set of values, wherein said subset of data signals assumes one of said first and second predetermined sets of values in response to said associated arrival times; and circuitry operable for modifying said preselected delay times in response to said first and second predetermined output signal values.

Claim 11

A data processing system including an interface comprising: a central processing unit (CPU); a receiving device coupled to said CPU operable for receiving at least one data signal from said CPU, said receiving device including a data receive unit comprising: a plurality of delay devices, each device being operable for receiving a corresponding data signal, each delay device having a preselectable delay time, and outputting said data signal after said preselected delay time; and circuitry coupled to said plurality of delay devices operable for setting each preselectable delay time, each preselected delay time being set in response to an arrival time associated with each data signal, wherein said circuitry operable for setting each preselectable delay time comprises: data compare logic operable for receiving a predetermined subset of said data signals, and outputting a first predetermined output signal value when said subset of data signals comprises a first predetermined set of values, and outputting a second predetermined output signal value when said subset of data signals has a second predetermined set of values, wherein said subset of data signals assumes one of said first and second predetermined sets of values in response to said associated arrival times; and circuitry operable for modifying said preselected delay times in response to said first and second predetermined output signal values.

Claim 12

The data processing system of claim 7 , wherein each preselectable delay time is selected in response to an initialization signal from said CPU.

Claim 13

The data processing system of claim 7 said circuitry operable for modifying said preselected delay times comprises: a state machine operable for modifying said preselected delay times in response to said first and second output signal values; a counter operable for receiving a direction signal from said state machine, said counter operable for outputting a count signal for determining a number of delay time increments for modifying said preselected delay times, wherein said delay time increment has a predetermined value; and delay control circuitry operable for receiving said count signal, and outputting a control signal to each of said plurality of delay devices, wherein said control signal is operable for modifying said preselected delay times.

Claim 14

The data processing system of claim 7 , wherein each preselectable delay time is selected in response to each data signal having a predetermined pattern of data values received from said CPU.