US5778214A
Expired / Lapsed
US
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Bit-phase aligning circuit
Assignee: Rateze Remote Mgmt LLC
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Filing: 1995-11-29
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Granted: 1998-07-07
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Expires: 2015-11-29
Abstract
Abstract A bit-phase aligning circuit includes a bit-phase adjusting circuit and a synchronizing pattern detection circuit. The bit-phase adjusting circuit adjusts a phase difference between a data signal and a clock signal by adjusting a delay amount of the data signal based on a determination result signal from the synchronizing pattern detection circuit. In the synchronizing pattern detection circuit, the data signal is sampled using the clock signal so as to detect a synchronizing pattern inserted in the data signal. When the synchronizing pattern is detected, the synchronizing pattern detection circuit determines that a phase relationship between the data signal and the clock signal is proper. On the other hand, when not detected, the synchronizing pattern detection circuit determines the phase relationship therebetween to be improper. This determination result signal is fed to the bit-phase adjusting circuit where the phase difference between the data signal and the clock signal is adjusted.
Inventors
- 👤 Takashi Taya
- 👤 Akira Yoshida
- 👤 Shinsuke Yamaoka
- 👤 Shuichi Matsumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:03
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337; H04L7/04; H04L7/041; H04L7/042; H04L7/10
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
186 words
A bit-phase aligning circuit comprising: bit-phase adjusting means for receiving input data containing therein a synchronizing pattern and adjusting a bit-phase difference between the input data and an input clock; and synchronizing pattern detection means for detecting said synchronizing pattern in the input data, determining whether a phase relationship between the input data and the input clock is proper or improper based on whether said synchronizing pattern is detected or not, controlling said bit-phase adjusting means to adjust said bit-phase difference based on the determination result, presetting a first phase difference adjusting range for an asynchronous state and a second phase difference adjusting range for a synchronous state, controlling said bit-phase adjusting means by setting the phase difference adjusting range to said first phase adjusting range when the asynchronous state is determined by said synchronizing pattern detection means, and controlling said bit-phase adjusting means by setting the phase difference adjusting range to said second phase difference adjusting range when the synchronous state is determined by said synchronizing pattern detection means; wherein said second phase difference adjusting range is greater than said first phase difference adjusting range.
Claim 2
Dependent Claim
186 words
A bit-phase aligning circuit comprising: bit-phase adjusting means for receiving input data containing therein a synchronizing pattern and adjusting a bit-phase difference between the input data and an input clock; and synchronizing pattern detection means for detecting said synchronizing pattern in the input data, determining whether a phase relationship between the input data and the input clock is proper or improper based on whether said synchronizing pattern is detected or not, controlling said bit-phase adjusting means to adjust said bit-phase difference based on the determination result, presetting a first phase difference adjusting range for an asynchronous state and a second phase difference adjusting range for a synchronous state, controlling said bit-phase adjusting means by setting the phase difference adjusting range to said first phase adjusting range when the asynchronous state is determined by said synchronizing pattern detection means, and controlling said bit-phase adjusting means by setting the phase difference adjusting range to said second phase difference adjusting range when the synchronous state is determined by said synchronizing pattern detection means; wherein said second phase difference adjusting range is greater than said first phase difference adjusting range.
Claim 3
Dependent Claim
45 words
The bit-phase aligning circuit according to claim 1, wherein said bit-phase adjusting means includes delaying means for delaying the input data in response to a control input from said synchronizing pattern detection means so as to adjust the bit-phase difference relative to the input clock.
Claim 4
Dependent Claim
45 words
The bit-phase aligning circuit according to claim 1, wherein said bit-phase adjusting means includes delaying means for delaying the input clock in response to a control input from said synchronizing pattern detection means so as to adjust the bit-phase difference relative to the input data.
Claim 5
Dependent Claim
76 words
The bit-phase aligning circuit according to claim 2, wherein said delaying means includes a delay element section for delaying the input data, including a plurality of delay elements connected in series relative to the input data, and selecting means, responsive to the control input from said synchronizing pattern detection means, for selecting the input data from a selected point in the serially-connected delay elements and providing the selected input data to said synchronizing pattern detection means.
Claim 6
Dependent Claim
76 words
The bit-phase aligning circuit according to claim 3, wherein said delaying means includes a delay element section for delaying the input clock, including a plurality of delay elements connected in series relative to the input clock, and selecting means, responsive to the control input from said synchronizing pattern detection means, for selecting the input clock from a selected point in the serially-connected delay elements and providing the selected input clock to said synchronizing pattern detection means.
Claim 7
Dependent Claim
98 words
The bit-phase aligning circuit according to claim 4, wherein said selecting means includes a plurality of electric circuit elements corresponding to said delay elements, wherein each of said electric circuit elements is capable of being turned on or off, and wherein said selecting means, responsive to the control input from said synchronizing pattern detection means, selects the input data from said selected point in the serially-connected delay elements and provides the selected input data to the synchronizing pattern detection means by rendering one of said electric circuit elements turned on and the other electric circuit elements turned off.
Claim 8
Dependent Claim
98 words
The bit-phase aligning circuit according to claim 5, wherein said selecting means includes a plurality of electric circuit elements corresponding to said delay elements, wherein each of said electric circuit elements is capable of being turned on or off, and wherein said selecting means, responsive to the control input from said synchronizing pattern detection means, selects the input clock from said selected point in the serially-connected delay elements and provides the selected input clock to the synchronizing pattern detection means by rendering one of said electric circuit elements turned on and the other electric circuit elements turned off.
Claim 9
Dependent Claim
118 words
A bit-phase alignment circuit, comprising: a bit-phase adjusting circuit for receiving input data containing therein a synchronizing pattern, adjusting a bit-phase difference between the input data and an input clock, and generating adjusted input data having the adjusted bit-phase difference; and a synchronizing pattern detection circuit for receiving the adjusted input data, for detecting the synchronizing pattern in the adjusted input data, determining whether a phase relationship between the adjusted input data and the input clock is proper or improper based on whether the synchronizing pattern is detected or not, and generating a determination result signal to the bit-phase adjusting circuit for controlling the bit-phase adjusting circuit to re-adjust the bit-phase difference based on the determination result signal.
Claim 10
Dependent Claim
118 words
A bit-phase alignment circuit, comprising: a bit-phase adjusting circuit for receiving input data containing therein a synchronizing pattern, adjusting a bit-phase difference between the input data and an input clock, and generating adjusted input data having the adjusted bit-phase difference; and a synchronizing pattern detection circuit for receiving the adjusted input data, for detecting the synchronizing pattern in the adjusted input data, determining whether a phase relationship between the adjusted input data and the input clock is proper or improper based on whether the synchronizing pattern is detected or not, and generating a determination result signal to the bit-phase adjusting circuit for controlling the bit-phase adjusting circuit to re-adjust the bit-phase difference based on the determination result signal.
Claim 11
Dependent Claim
133 words
The bit-phase alignment circuit according to claim 8, wherein: the synchronizing pattern detection circuit includes a first check circuit for receiving the adjusted input data and the input clock, a second check circuit for receiving the adjusted input data delayed by a first delay element, and the input clock, and a third check circuit for receiving the adjusted input data delayed by the first delay element and a second delay element, and the input clock; and the synchronizing pattern detection circuit detects the synchronizing pattern from the received adjusted input data and determines whether the adjusted input data is in a synchronized, forward, or backward phase relationship with respect to the input clock, based on whether the synchronizing pattern is detected or not at each of the first, second, and third check circuits.
Claim 12
Dependent Claim
137 words
A bit-phase alignment circuit, comprising: a bit-phase adjusting circuit for receiving input data containing therein a synchronizing pattern, adjusting a bit-phase difference between the input data and an input clock, and generating adjusted input data having the adjusted bit-phase difference, wherein the synchronizing pattern includes a bit sequence arranged periodically in the input data according to a predetermined rule; and a synchronizing pattern detection circuit for receiving the adjusted input data, for detecting the synchronizing pattern in the adjusted input data, determining whether a phase relationship between the adjusted input data and the input clock is proper or improper based on whether the synchronizing pattern is detected or not, and generating a determination result signal to the bit-phase adjusting circuit for controlling the bit-phase adjusting circuit to re-adjust the bit-phase difference based on the determination result signal.
Claim 13
Dependent Claim
137 words
A bit-phase alignment circuit, comprising: a bit-phase adjusting circuit for receiving input data containing therein a synchronizing pattern, adjusting a bit-phase difference between the input data and an input clock, and generating adjusted input data having the adjusted bit-phase difference, wherein the synchronizing pattern includes a bit sequence arranged periodically in the input data according to a predetermined rule; and a synchronizing pattern detection circuit for receiving the adjusted input data, for detecting the synchronizing pattern in the adjusted input data, determining whether a phase relationship between the adjusted input data and the input clock is proper or improper based on whether the synchronizing pattern is detected or not, and generating a determination result signal to the bit-phase adjusting circuit for controlling the bit-phase adjusting circuit to re-adjust the bit-phase difference based on the determination result signal.
Claim 14
Dependent Claim
133 words
The bit-phase alignment circuit according to claim 10, wherein: the synchronizing pattern detection circuit includes a first check circuit for receiving the adjusted input data and the input clock, a second check circuit for receiving the adjusted input data delayed by a first delay element, and the input clock, and a third check circuit for receiving the adjusted input data delayed by the first delay element and a second delay element, and the input clock; and the synchronizing pattern detection circuit detects the synchronizing pattern from the received adjusted input data and determines whether the adjusted input data is in a synchronized, forward, or backward phase relationship with respect to the input clock, based on whether the synchronizing pattern is detected or not at each of the first, second, and third check circuits.
References Cited (Backward Citations)
US4756011A
Cited
US4773085A
Cited
US4821296A
Cited
JPH02228839A
Cited
US5081655A
Cited
US5134636A
Cited
JPH04293332A
Cited
US5278873A
Cited
JPH05219040A
Cited
US5550860A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-07-06 | 2002-01-05 | 2002-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-06 | 2006-01-05 | 2006-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-06 | 2010-01-05 | 2010-07-07 | $7700.00 | Window Closed / Lapsed |