US5134636A
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Synchronization circuit for a synchronous switching system
Assignee: Cisco Technology Inc
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Filing: 1991-02-20
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Granted: 1992-07-28
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Expires: 2011-02-20
Abstract
Abstract The synchronization circuit resynchronizes the data bits received from remote devices on line or link (20-1) with their own clock CS and frame synchronization signal FS with a central clock CO and central frame synchronization signal FO. The received bits are sequentially arranged in an n-bit cyclic buffer (114-1) with the received bit clock CS. The arranged bits are sequentially picked at the opposite buffer position with the central clock CO. The buffer loading position is provided by binary counter 102 incremented by CS and the buffer picking portion is given by binary counter 100 incremented by CO. At initialization counters 102 and 100 are set to 0 and n/2. The resynchronized data bits on line 21-1 and the resynchronized frame signal FSR on line 61-10 are provided to an additional circuit which synchronize the data bits at the frame level.
Inventors
- 👤 Gerard Barucchi
- 👤 Jean Calvignac
- 👤 Jose Galcera
- 👤 Gilles Toubol
- 👤 Andre Tracol
- 👤 Daniel Orsatti
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:40
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626; H04J3/0629
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
283 words
A synchronization circuit receiving data bits on an input line or link (20-1) at the frequency of the pulses of a first clock signal (CS) and providing said data bits on a first output line or link (21-1) at the frequency of the pulses of a second clock signal (CO) having any phase relationship with the first clock signal, characterized in that it comprises: first counting means (102) which counts modulo-n the pulses of the first clock signal, n being an integer number at least equal to 2, second counting means (100) which counts modulo-n the pulses of the second clock signal, a first buffering means (114-1) having n stages first gating means (113-1) responsive to the values reached by the first counting means for cyclically gating the received bits for storage in the stages of the first buffering means in a first predetermined sequence, the number of the stage into which a received bit is gated being determined by a first relationship established between the numbers of the stages and the values reached by the first counting means, second gating means (119-1, 120-1) responsive to the values reached by the second counting means for cyclically gating the bits stored in the stages of the first buffering means on the first output line in a second predetermined sequence, the number of the stage from which a bit is gated on the output line being determined by a second relationship between the numbers of the stages and the values reached by the second counting means, so that the bits are provided on the first output line at the frequency of the pulses of the second clock signal in the same order they are received.
Claim 2
Dependent Claim
283 words
A synchronization circuit receiving data bits on an input line or link (20-1) at the frequency of the pulses of a first clock signal (CS) and providing said data bits on a first output line or link (21-1) at the frequency of the pulses of a second clock signal (CO) having any phase relationship with the first clock signal, characterized in that it comprises: first counting means (102) which counts modulo-n the pulses of the first clock signal, n being an integer number at least equal to 2, second counting means (100) which counts modulo-n the pulses of the second clock signal, a first buffering means (114-1) having n stages first gating means (113-1) responsive to the values reached by the first counting means for cyclically gating the received bits for storage in the stages of the first buffering means in a first predetermined sequence, the number of the stage into which a received bit is gated being determined by a first relationship established between the numbers of the stages and the values reached by the first counting means, second gating means (119-1, 120-1) responsive to the values reached by the second counting means for cyclically gating the bits stored in the stages of the first buffering means on the first output line in a second predetermined sequence, the number of the stage from which a bit is gated on the output line being determined by a second relationship between the numbers of the stages and the values reached by the second counting means, so that the bits are provided on the first output line at the frequency of the pulses of the second clock signal in the same order they are received.
Claim 3
Dependent Claim
35 words
A synchronization circuit according to claim 1, characterized in that the first and second counting means are initially set at values which differ by an integer number x which is equal or higher than n/2.
Claim 4
Dependent Claim
15 words
A synchronization circuit according to claim 2, characterized in that n is equal to 4.
Claim 5
Dependent Claim
19 words
A synchronization circuit according to claim 2 or 3, characterized in that the first and second relationships are identical.
Claim 6
Dependent Claim
58 words
A synchronization circuit according to claim 1 further including a frame synchronizing means for receiving bits on the first output line (21-1) packaged into frames delimited by pulses of a first frame synchronization signal and for providing said data bits on a second output line (80) packaged into frames delimited by pulses of a second frame synchronization signal.
Claim 7
Dependent Claim
25 words
The synchronization circuit of claim 5 wherein the bits on the first output line are being received at the frequency of the first clock signal.
Claim 8
Dependent Claim
20 words
The synchronization circuit of claim 6 wherein the first frame synchronization signal is being derived from the first clock signal.
Claim 9
Dependent Claim
25 words
The synchronization circuit of claim 7 wherein the bits on the second output lone (80) are provided at the frequency of the second clock signal.
Claim 10
Dependent Claim
23 words
The synchronization circuit of claim 8 wherein the frequency of the first frame synchronization signal and second frame synchronization signal are the same.
Claim 11
Dependent Claim
102 words
The synchronization circuit of claim 5 wherein the frame synchronization include a second buffering means (114-FS) having n stages, third gating means (113-FS) responsive to the values reached by the first counting means for gating the pulses of the first frame synchronization signal in the stages of the second buffer determined by the first relationship, and fourth gating means (119-FS, 120-FS) responsive to the values reached by the second counting means for gating the pulses stored in the stages of the second buffering means determined by the second relationship and thus providing a resynchronized frame signal on a resynchronized frame line (61-10).
Claim 12
Dependent Claim
66 words
The synchronization circuitry of claim 10 wherein the frame synchronization means further includes a frame resynchronization circuit (150, 162) connected to the frame resynchronized line and to the first output line and responsive to the second frame synchronization signal for aligning the data bits from the first output line with the second frame synchronization pulses and provided the so-aligned data bits on the second output line.
Claim 13
Dependent Claim
201 words
A synchronization circuit according to claim 11, characterized in that the frame resynchronization circuit comprises: a first p-stage shift register (151-1) into which the data bits from the first output line (21-1) are inputted and shifted under control of the second clock signal (CO), p being an integer number higher than 2, a second p-stage shift register (164) into which the resynchronized frame signal is inputted and shifted under control of the second clock signal, measuring means (169) responsive to the second frame synchronization signal and to the resynchronized frame signal at the input of the second shift register and to the delayed frame resynchronization signal at the output of each stage of the second shift register to measure the number of the clock pulses of the second clock signal separating the second frame synchronization pulse and the resynchronized frame pulse, at the beginning of each frame; and fifth gating means (156) responsive to the measure performed by the measuring means to gate the data bits from the first output line or the delayed data bits at an output of a selected stage of the first shift register on the second output line depending upon the measured number of clock pulses.
Claim 14
Dependent Claim
125 words
A frame synchronization circuit arrangement comprising: a first circuit means for receiving data bits on a first input line at a first frequency of a first clock signal and for generating delayed data bits from said data bits; a control means for generating control signals; said control means generating said control signals in response to signals including the first clock signal and a first frame synchronization pulse delimiting frame at the first frequency and a second circuit means responsive to the control signals and operable for correlating the delayed data bits and the data bits to generate output data bits on a second output line (80) at a frequency of a second clock signal in frame delimited by pulses of a second frame synchronization signal.
Claim 15
Dependent Claim
125 words
A frame synchronization circuit arrangement comprising: a first circuit means for receiving data bits on a first input line at a first frequency of a first clock signal and for generating delayed data bits from said data bits; a control means for generating control signals; said control means generating said control signals in response to signals including the first clock signal and a first frame synchronization pulse delimiting frame at the first frequency and a second circuit means responsive to the control signals and operable for correlating the delayed data bits and the data bits to generate output data bits on a second output line (80) at a frequency of a second clock signal in frame delimited by pulses of a second frame synchronization signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-28 | 1996-01-27 | 1996-07-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-28 | 2000-01-27 | 2000-07-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-28 | 2004-01-27 | 2004-07-28 | $7700.00 | Window Closed / Lapsed |