Synchronization method and synchronization recovery devices for half-duplex communication

Claim 3

A synchronization recovery device included in one of ends of a half-duplex bidirectional link and receiving a communication signal transmitted from the other link end and through said link, said signal comprising first and second time intervals, said first time intervals beginning with a predetermined digital synchronization pattern followed by useful data, said second time intervals being devoid of useful data and in a first logic state, said synchronization pattern including at least a bit in a second logic state which is complementary to said first logic state, said device comprising first means for detecting in said communication signal, sequences of bits in the first logic state with duration equal to at least the duration of said second time intervals, second means for detecting said synchronization pattern in said communication signal, and means connected to said first and second detecting means for deriving a synchronization pulse when said synchronization pattern is detected immediately after one of said bit sequences.

Claim 4

A synchronization recovery device included in one of ends of a half-duplex bidirectional link and receiving a communication signal transmitted from the other link end and through said link, said signal comprising first and second time intervals, said first time intervals beginning with a predetermined digital synchronization pattern followed by useful data, said second time intervals being devoid of useful data and in a first logic state, said synchronization pattern including at least a bit in a second logic state which is complementary to said first logic state, said device comprising first means for detecting in said communication signal, sequences of bits in the first logic state with duration equal to at least the duration of said second time intervals, second means for detecting said synchronization pattern in said communication signal, and means connected to said first and second detecting means for deriving a synchronization pulse when said synchronization pattern is detected immediately after one of said bit sequences.

Claim 5

The device of claim 2 wherein said first detecting means comprises a binary counter which is incremented by bit rate signal pulses corresponding to said communication signal and means for resetting said counter by bits contained in said first time intervals and in said second logic state.

Claim 6

The device of claim 2 comprising means connected to said deriving means for detecting an absence of said synchronization pulse during a predetermined number of successive periods each including one first time interval and one second time interval thereby signalling a synchronization anomaly.

Claim 9

The method of claim 5 wherein N is much less than N 1 or N 2 .

Claim 10

The method of claim 5 wherein each of said frames has a predetermined duration, and signalling that the frame alignment has been lost in response to frame alignment not being detected for a predetermined period of time associated with N 3 frames, where N 3 is an integer greater than one.

Claim 11

The method of claim 5 wherein the presence of the sequential N 1 bits of the first interval having said predetermined value is detected by: (a) supplying at least N 1 clock pulses having the same frequency as the bits to a modulo N 1 counter at the second terminal, (b) supplying a replica of the bits as received at the second terminal to a reset input of the counter so that the counter is in an overflow state when all of the bits of the first interval have been received at the second terminal, and (c) detecting the overflow condition of the counter.

Claim 12

The method of claim 8 wherein the presence of the first N bits of the second interval having the predetermined sequence is detected by supplying a replica of the bits as received at the second terminal to a shift register having N stages, and deriving an enable signal when the contents of the shift register are the same as the values of the bits in the predetermined sequence; and sensing the simultaneous presence of the enable signal and the overflow condition to signal that frame alignment is present.

Claim 13

The method of claim 9 further including supplying the bits at the last stage of the shift register to the reset input of the counter.

Claim 14

The method of claim 8 wherein the presence of the first N bits of the second interval having the predetermined sequence is detected by supplying a replica of the bits as received at the second terminal to a shift register having N stages, and deriving an enable signal when the contents of the shift register are the same as the values of the bits in the predetermined sequence.

Claim 15

Apparatus for synchronizing a message transmitted from a first terminal to a second terminal via a half-duplex bi-directional link wherein the message is synchronized at the second terminal in response to bits received at the second terminal from the first terminal via the half-duplex bi-directional link, the first terminal forming sequential communication frames each including first and second abutting sequential time intervals respectively having N 1 and N 2 serial bits, each of said bits having the same predetermined time duration so that the first and second intervals respectively have first and second time durations, the last bit of each first interval preceding immediately before the first bit of the next following second interval, all of the N 1 bits of each first interval having the same predetermined value that is independent of the message content, the first N bits of each second interval having a predetermined binary sequence including at least one bit having a value different from the value of the bits of the first interval, where each of N, N 1 and N 2 is an integer greater than one, the remaining bits of each second interval being determined by the message, the second terminal comprising means responsive to the bits in the first and second time intervals as received at the second terminal for indicating that frame alignment for the frame is present, said last named means including means for detecting the presence of the sequential N 1 bits of the first interval having said predetermined value followed immediately by the first N bits of the second interval having the predetermined sequence.

Claim 16

Apparatus for synchronizing a message transmitted from a first terminal to a second terminal via a half-duplex bi-directional link wherein the message is synchronized at the second terminal in response to bits received at the second terminal from the first terminal via the half-duplex bi-directional link, the first terminal forming sequential communication frames each including first and second abutting sequential time intervals respectively having N 1 and N 2 serial bits, each of said bits having the same predetermined time duration so that the first and second intervals respectively have first and second time durations, the last bit of each first interval preceding immediately before the first bit of the next following second interval, all of the N 1 bits of each first interval having the same predetermined value that is independent of the message content, the first N bits of each second interval having a predetermined binary sequence including at least one bit having a value different from the value of the bits of the first interval, where each of N, N 1 and N 2 is an integer greater than one, the remaining bits of each second interval being determined by the message, the second terminal comprising means responsive to the bits in the first and second time intervals as received at the second terminal for indicating that frame alignment for the frame is present, said last named means including means for detecting the presence of the sequential N 1 bits of the first interval having said predetermined value followed immediately by the first N bits of the second interval having the predetermined sequence.

Claim 17

The apparatus of claim 12 wherein N is much less than N 1 or N 2 .

Claim 18

The apparatus of claim 12 wherein each of said frames has a predetermined duration, and means at the second terminal for signalling that frame alignment has been lost in response to frame alignment not being detected for a predetermined period of time associated with N 3 frames, where N 3 is an integer greater than one.

Claim 19

The apparatus of claim 14 wherein the means for signalling that frame alignment has been lost comprises N 3 cascaded register stages responsive to clock pulses having a period equal to the duration of one of said frames and to a signal indicating the presence of frame alignment derived from the means for indicating frame alignment.

Claim 20

The apparatus of claim 12 wherein the means for detecting the presence of sequential N 1 sequential bits of the first interval having said predetermined value includes a modulo N 1 counter having a clock input responsive to clock pulses having the same frequency as the bits and a reset input responsive to the bits in the first and second time intervals and an overflow output on which is derived a first enable signal in response to N 1 consecutive binary bits having the predetermined value being supplied to the reset input.

Claim 21

The apparatus of claim 16 wherein the means for detecting the presence of the sequential N 1 bits of the first interval having said predetermined value followed immediately by the first N bits of the second interval having the predetermined sequence includes a shift register having N stages responsive to the bits of the first and second intervals, the reset input of the modulo N 1 counter being responsive to bits derived from stage N of the shift register, means for deriving a second enable signal in response to the contents of the shift register correlating with the N bits having values representing the predetermined binary sequence, and means responsive to the simultaneous derivation of the first and second enable signals for indicating that frame alignment is present.

Claim 22

The apparatus of claim 17 further including means for signalling that frame alignment has been lost, said last named means comprising N 3 cascaded register stages responsive to clock pulses having a period equal to the duration of one of said frames and to a signal indicating the presence of frame alignment derived from the means for indicating frame alignment.

Claim 23

The apparatus of claim 18 wherein each of the cascaded register stages includes a D flip-flop having a Q output, D input, a reset input responsive to the signal indicating the presence of frame alignment, a clock input responsive to the clock pulses having a period equal to the duration of one of said frames, the D input of the D flip-flop of stage P being responsive to the Q output of stage (P-1), where P=2 . . . N 3 , the D input of the flip-flop of stage 1 being responsive to a predetermined level.