Patent US6636093B1 successfully refreshed from Google Patents.
US6636093B1
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Compensation for a delay locked loop
Assignee: Round Rock Research LLC
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Filing: 2000-07-14
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Granted: 2003-10-21
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Expires: 2020-07-14
Abstract
Abstract A method and apparatus for compensating a delay locked loop against signal timing variances after circuit initialization which cause delay shifts due to temperature and voltage changes and operational noise. A delay line of a delay locked loop is disclosed, the delay line having a plurality of delay elements and a minimum and maximum delay boundary. According to an embodiment of the invention, an artificial minimum or maximum boundary, or both, is established on the delay line such that during initialization of the delay locked loop circuit, the circuit cannot lock on a delay element beyond the artificial minimum or maximum boundaries. By offsetting the artificial minimum and maximum boundaries from the actual minimum and maximum boundaries of the delay line, a buffer of delay elements is established at the actual delay line boundaries. During operation of the delay locked loop apart from initialization, the artificial boundaries become transparent to the delay locked loop and are available for the circuitry to use if needed.
Inventors
- 👤 Eric T. Stubbs
- 👤 Christopher K. Morzano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:41
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1066; G11C7/22; G11C7/222; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816; H03L7/10
Claims Analysis
Total Claims: 45
Claim 1
Independent Claim
103 words
A delay line of a delay locked loop, the delay line comprising: a plurality of directly coupled delay elements; a minimum delay boundary adjacent a first delay element of the plurality of delay elements and a maximum delay boundary adjacent a second delay element of the plurality of delay elements; at least one delay element adjacent to the minimum delay boundary and operably coupled to the plurality of delay elements through at least one multiplexer; and at least one other delay element adjacent to the maximum delay boundary and operably coupled to the plurality of delay elements through at least one other multiplexer.
Claim 2
Dependent Claim
103 words
A delay line of a delay locked loop, the delay line comprising: a plurality of directly coupled delay elements; a minimum delay boundary adjacent a first delay element of the plurality of delay elements and a maximum delay boundary adjacent a second delay element of the plurality of delay elements; at least one delay element adjacent to the minimum delay boundary and operably coupled to the plurality of delay elements through at least one multiplexer; and at least one other delay element adjacent to the maximum delay boundary and operably coupled to the plurality of delay elements through at least one other multiplexer.
Claim 3
Dependent Claim
72 words
A delay line of a delay locked loop, the delay line comprising: a plurality of directly coupled delay elements; a minimum delay boundary adjacent to a first end of the delay line and a maximum delay boundary adjacent to a second end of the delay line; and at least one delay element adjacent to the maximum delay boundary and operably coupled to the plurality of delay elements through at least one multiplexer.
Claim 4
Dependent Claim
72 words
A delay line of a delay locked loop, the delay line comprising: a plurality of directly coupled delay elements; a minimum delay boundary adjacent to a first end of the delay line and a maximum delay boundary adjacent to a second end of the delay line; and at least one delay element adjacent to the maximum delay boundary and operably coupled to the plurality of delay elements through at least one multiplexer.
Claim 5
Dependent Claim
84 words
A delay line of a delay locked loop, the delay line comprising: a plurality of directly coupled delay elements; and at least one delay element operably coupled to the plurality of delay elements through at least one multiplexer, wherein the at least one multiplexer is configured to generate at least one artificial boundary within the delay line to preclude delay locked loop circuitry associated with the delay line from locking on the at least one delay element beyond the at least one artificial boundary.
Claim 6
Dependent Claim
84 words
A delay line of a delay locked loop, the delay line comprising: a plurality of directly coupled delay elements; and at least one delay element operably coupled to the plurality of delay elements through at least one multiplexer, wherein the at least one multiplexer is configured to generate at least one artificial boundary within the delay line to preclude delay locked loop circuitry associated with the delay line from locking on the at least one delay element beyond the at least one artificial boundary.
Claim 7
Dependent Claim
32 words
The delay line of claim 3 , wherein the at least one multiplexer is configured to generate the at least one artificial boundary only during initialization of the delay locked loop circuitry.
Claim 8
Dependent Claim
75 words
A delay locked loop comprising: a plurality of directly coupled delay elements having a maximum delay element and a minimum delay element at each end; first circuitry configured to select at least one delay element from among any of the plurality of delay elements; and second circuitry configured to preclude the first circuitry from selecting at least one of the maximum delay element and the minimum delay element from among the plurality of delay elements.
Claim 9
Dependent Claim
75 words
A delay locked loop comprising: a plurality of directly coupled delay elements having a maximum delay element and a minimum delay element at each end; first circuitry configured to select at least one delay element from among any of the plurality of delay elements; and second circuitry configured to preclude the first circuitry from selecting at least one of the maximum delay element and the minimum delay element from among the plurality of delay elements.
Claim 10
Dependent Claim
38 words
The delay locked loop of claim 5 , wherein the second circuitry comprises circuitry configured to preclude the first circuitry from selecting the at least one of the maximum delay element and the minimum delay element during initialization.
Claim 11
Dependent Claim
16 words
The delay locked loop of claim 5 , wherein the first circuitry comprises a shift register.
Claim 12
Dependent Claim
70 words
A delay locked loop comprising: a plurality of directly coupled delay elements; first circuitry configured to select at least one delay element from among the plurality of delay elements; and second circuitry configured to preclude the first circuitry from selecting at least one other delay element operably coupled to the plurality of delay elements, wherein the second circuitry comprises at least one multiplexer responsive to at least one control signal.
Claim 13
Dependent Claim
70 words
A delay locked loop comprising: a plurality of directly coupled delay elements; first circuitry configured to select at least one delay element from among the plurality of delay elements; and second circuitry configured to preclude the first circuitry from selecting at least one other delay element operably coupled to the plurality of delay elements, wherein the second circuitry comprises at least one multiplexer responsive to at least one control signal.
Claim 14
Dependent Claim
99 words
A delay locked loop comprising: a plurality of directly coupled delay elements; first circuitry configured to select at least one delay element from among the plurality of delay elements; and second circuitry configured to preclude the first circuitry from selecting at least one other delay element operably coupled to the plurality of delay elements, wherein the second circuitry is further configured to allow the at least one other delay element to be selected in response to an indication from phase comparator circuitry associated with the second circuitry that a delay signal is substantially in phase with a reference signal.
Claim 15
Dependent Claim
99 words
A delay locked loop comprising: a plurality of directly coupled delay elements; first circuitry configured to select at least one delay element from among the plurality of delay elements; and second circuitry configured to preclude the first circuitry from selecting at least one other delay element operably coupled to the plurality of delay elements, wherein the second circuitry is further configured to allow the at least one other delay element to be selected in response to an indication from phase comparator circuitry associated with the second circuitry that a delay signal is substantially in phase with a reference signal.
Claim 16
Dependent Claim
106 words
An electronic circuit including at least one delay line of a delay locked loop comprising: a plurality of directly coupled delay elements; a minimum delay boundary adjacent a first delay element of the plurality of delay elements and a maximum delay boundary adjacent a second delay element of the plurality of delay elements; at least one delay element adjacent to the minimum delay boundary and operably coupled to the plurality of delay elements through at least one multiplexer; and at least one other delay element adjacent to the maximum delay boundary and operably coupled to the plurality of delay elements through at least one other multiplexer.
Claim 17
Dependent Claim
106 words
An electronic circuit including at least one delay line of a delay locked loop comprising: a plurality of directly coupled delay elements; a minimum delay boundary adjacent a first delay element of the plurality of delay elements and a maximum delay boundary adjacent a second delay element of the plurality of delay elements; at least one delay element adjacent to the minimum delay boundary and operably coupled to the plurality of delay elements through at least one multiplexer; and at least one other delay element adjacent to the maximum delay boundary and operably coupled to the plurality of delay elements through at least one other multiplexer.
Claim 18
Dependent Claim
81 words
An electronic circuit including at least one delay line of a delay locked loop comprising: a plurality of directly coupled delay elements; a minimum delay boundary adjacent to a first end of the at least one delay line and a maximum delay boundary adjacent to a second end of the at least one delay line; and at least one delay element adjacent to the maximum delay boundary and operably coupled to the plurality of delay elements through at least one multiplexer.
Claim 19
Dependent Claim
81 words
An electronic circuit including at least one delay line of a delay locked loop comprising: a plurality of directly coupled delay elements; a minimum delay boundary adjacent to a first end of the at least one delay line and a maximum delay boundary adjacent to a second end of the at least one delay line; and at least one delay element adjacent to the maximum delay boundary and operably coupled to the plurality of delay elements through at least one multiplexer.
Claim 20
Dependent Claim
93 words
An electronic circuit including at least one delay line of a delay locked loop comprising: a plurality of directly coupled delay elements; and at least one delay element operably coupled to the plurality of delay elements through at least one multiplexer, wherein the at least one multiplexer is configured to generate at least one artificial boundary within the at least one delay line to preclude delay locked loop circuitry associated with the at least one delay line from locking on the at least one delay element beyond the at least one artificial boundary.
Claim 21
Dependent Claim
93 words
An electronic circuit including at least one delay line of a delay locked loop comprising: a plurality of directly coupled delay elements; and at least one delay element operably coupled to the plurality of delay elements through at least one multiplexer, wherein the at least one multiplexer is configured to generate at least one artificial boundary within the at least one delay line to preclude delay locked loop circuitry associated with the at least one delay line from locking on the at least one delay element beyond the at least one artificial boundary.
Claim 22
Dependent Claim
32 words
The electronic circuit of claim 12 , wherein the at least one multiplexer is configured to generate the at least one artificial boundary only during initialization of the delay locked loop circuitry.
Claim 23
Dependent Claim
120 words
An electronic system comprising: a processor; and at least one of an input device, an output device and a data storage device associated with the processor; wherein at least one component of the electronic system comprises: a plurality of delay elements directly coupled as a delay line of a delay locked loop, the plurality of delay elements having a maximum delay element and a minimum delay element at each end; first circuitry configured to select at least one delay element from among any of the plurality of delay elements; and second circuitry configured to preclude the first circuitry from selecting at least one of the maximum delay element and the minimum delay element from among the plurality of delay elements.
Claim 24
Dependent Claim
120 words
An electronic system comprising: a processor; and at least one of an input device, an output device and a data storage device associated with the processor; wherein at least one component of the electronic system comprises: a plurality of delay elements directly coupled as a delay line of a delay locked loop, the plurality of delay elements having a maximum delay element and a minimum delay element at each end; first circuitry configured to select at least one delay element from among any of the plurality of delay elements; and second circuitry configured to preclude the first circuitry from selecting at least one of the maximum delay element and the minimum delay element from among the plurality of delay elements.
Claim 25
Dependent Claim
37 words
The electronic system of claim 14 , wherein the second circuitry comprises circuitry configured to preclude the first circuitry from selecting the at least one of the maximum delay element and the minimum delay element during initialization.
Claim 26
Dependent Claim
15 words
The electronic system of claim 14 , wherein the first circuitry comprises a shift register.
Claim 27
Dependent Claim
110 words
An electronic system comprising: a processor; and at least one of an input device, an output device and a data storage device associated with the processor; wherein at least one component of the electronic system comprises: a plurality of delay elements directly coupled as a delay line of a delay locked loop; first circuitry configured to select at least one delay element from among the plurality of delay elements; and second circuitry configured to preclude the first circuitry from selecting at least one other delay element operably coupled to the plurality of delay elements, wherein the second circuitry comprises at least one multiplexer responsive to at least one control signal.
Claim 28
Dependent Claim
110 words
An electronic system comprising: a processor; and at least one of an input device, an output device and a data storage device associated with the processor; wherein at least one component of the electronic system comprises: a plurality of delay elements directly coupled as a delay line of a delay locked loop; first circuitry configured to select at least one delay element from among the plurality of delay elements; and second circuitry configured to preclude the first circuitry from selecting at least one other delay element operably coupled to the plurality of delay elements, wherein the second circuitry comprises at least one multiplexer responsive to at least one control signal.
Claim 29
Dependent Claim
139 words
An electronic system comprising: a processor; and at least one of an input device, an output device and a data storage device associated with the processor; wherein at least one component of the electronic system comprises: a plurality of delay elements directly coupled as a delay line of a delay locked loop; first circuitry configured to select at least one delay element from among the plurality of delay elements; and second circuitry configured to preclude the first circuitry from selecting at least one other delay element operably coupled to the plurality of delay elements, wherein the second circuitry is further configured to allow the at least one other delay element to be selected in response to an indication from phase comparator circuitry associated with the second circuitry that a delay signal is substantially in phase with a reference signal.
Claim 30
Dependent Claim
139 words
An electronic system comprising: a processor; and at least one of an input device, an output device and a data storage device associated with the processor; wherein at least one component of the electronic system comprises: a plurality of delay elements directly coupled as a delay line of a delay locked loop; first circuitry configured to select at least one delay element from among the plurality of delay elements; and second circuitry configured to preclude the first circuitry from selecting at least one other delay element operably coupled to the plurality of delay elements, wherein the second circuitry is further configured to allow the at least one other delay element to be selected in response to an indication from phase comparator circuitry associated with the second circuitry that a delay signal is substantially in phase with a reference signal.
Claim 31
Dependent Claim
110 words
A semiconductor wafer including circuitry fabricated thereon, the circuitry comprising: a plurality of delay elements directly coupled as a delay line of a delay locked loop; a minimum delay boundary adjacent a first delay element of the plurality of delay elements and a maximum delay boundary adjacent a second delay element of the plurality of delay elements; at least one delay element adjacent to the minimum delay boundary and operably coupled to the plurality of delay elements through at least one multiplexer; and at least one other delay element adjacent to the maximum delay boundary and operably coupled to the plurality of delay elements through at least one other multiplexer.
Claim 32
Dependent Claim
110 words
A semiconductor wafer including circuitry fabricated thereon, the circuitry comprising: a plurality of delay elements directly coupled as a delay line of a delay locked loop; a minimum delay boundary adjacent a first delay element of the plurality of delay elements and a maximum delay boundary adjacent a second delay element of the plurality of delay elements; at least one delay element adjacent to the minimum delay boundary and operably coupled to the plurality of delay elements through at least one multiplexer; and at least one other delay element adjacent to the maximum delay boundary and operably coupled to the plurality of delay elements through at least one other multiplexer.
Claim 33
Dependent Claim
90 words
A semiconductor wafer including circuitry fabricated thereon, the circuitry comprising: a plurality of delay elements directly coupled as a delay line of a delay locked loop; at least one delay element operably coupled to the plurality of delay elements through at least one multiplexer, wherein the at least one multiplexer is configured to generate at least one artificial boundary within the delay line to preclude delay locked loop circuitry associated with the delay line from locking on the at least one delay element beyond the at least one artificial boundary.
Claim 34
Dependent Claim
90 words
A semiconductor wafer including circuitry fabricated thereon, the circuitry comprising: a plurality of delay elements directly coupled as a delay line of a delay locked loop; at least one delay element operably coupled to the plurality of delay elements through at least one multiplexer, wherein the at least one multiplexer is configured to generate at least one artificial boundary within the delay line to preclude delay locked loop circuitry associated with the delay line from locking on the at least one delay element beyond the at least one artificial boundary.
Claim 35
Dependent Claim
32 words
The semiconductor wafer of claim 20 , wherein the at least one multiplexer is configured to generate the at least one artificial boundary only during initialization of the delay locked loop circuitry.
Claim 36
Independent Claim
47 words
A method of initializing a delay locked loop, the method comprising: receiving an initialization signal; establishing at least one artificial boundary on a delay line of the delay locked loop; and selecting a delay setting for the delay locked loop within the at least one artificial boundary.
Claim 37
Independent Claim
47 words
A method of initializing a delay locked loop, the method comprising: receiving an initialization signal; establishing at least one artificial boundary on a delay line of the delay locked loop; and selecting a delay setting for the delay locked loop within the at least one artificial boundary.
Claim 38
Dependent Claim
21 words
The method of claim 22 , further comprising: receiving a phase lock signal; and removing the at least one artificial boundary.
Claim 39
Dependent Claim
44 words
The method of claim 22 , wherein establishing the at least one artificial boundary comprises causing a delay element which is not adjacent to an end of the delay line to appear as though it is adjacent to the end of the delay line.
Claim 40
Independent Claim
56 words
A method of synchronizing the phases of a delayed signal and a reference signal, the method including initializing a delay locked loop, the initialization comprising: establishing at least one buffer region on a delay line of the delay locked loop; and selecting a delay setting along the delay line outside the at least one buffer region.
Claim 41
Independent Claim
56 words
A method of synchronizing the phases of a delayed signal and a reference signal, the method including initializing a delay locked loop, the initialization comprising: establishing at least one buffer region on a delay line of the delay locked loop; and selecting a delay setting along the delay line outside the at least one buffer region.
Claim 42
Dependent Claim
15 words
The method of claim 25 , further comprising removing the at least one buffer region.
Claim 43
Dependent Claim
20 words
The method of claim 26 , wherein the at least one buffer region is removed upon completion of the initialization.
Claim 44
Dependent Claim
41 words
The method of claim 25 , further comprising shifting into the at least one buffer region to adjust for a signal timing change resulting from at least one of a temperature change, a signal voltage change and a signal noise change.
Claim 45
Dependent Claim
76 words
The method of claim 25 , wherein the delay locked loop comprises a plurality of delay elements including a first portion forming the at least one buffer region and a second portion forming a remainder of the plurality of delay elements, the method further comprising: resetting the first portion of the plurality of delay elements to a value of 1; and resetting the second portion of the plurality of delay elements to a value of 0.
References Cited (Backward Citations)
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