Patent US6635543B2 successfully refreshed from Google Patents.
← Back to Patent Explorer
US6635543B2 Expired / Lapsed US ⏱️ 0.0 years remaining

SOI hybrid structure with selective epitaxial growth of silicon

Assignee: GlobalFoundries Inc
•
Filing: 2002-12-31
•
Granted: 2003-10-21
•
Expires: 2022-12-31
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.

Inventors

  • 👤 Toshiharu Furukawa
  • 👤 Jack A. Mandelman
  • 👤 Dan Moy
  • 👤 Byeongju Park
  • 👤 William R. Tonti

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 23:52
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/09; H10D; H10D86/00; H10D86/01; H10D87/00; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10B12/02; H10B12/03; H10B12/038; H10P90/1912

Claims Analysis

Total Claims: 28
Claim 1
Independent Claim 115 words
A method for forming an electronic structure, comprising the steps of: forming a silicon-on-insulator (SOI) structure having a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX; anisotropically etching the SOI structure to form a trench through the silicon layer, through the BOX, and through a depth D of the silicon substrate, wherein D≧0; forming insulative spacers on sidewalls of the trench; and growing an epitaxial layer of silicon or silicon-germanium alloy in the trench from a bottom of the trench to a height at or above the silicon layer, wherein the insulative spacers provide electrical insulation between the silicon layer outside the trench and the epitaxial layer.
Claim 2
Independent Claim 115 words
A method for forming an electronic structure, comprising the steps of: forming a silicon-on-insulator (SOI) structure having a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX; anisotropically etching the SOI structure to form a trench through the silicon layer, through the BOX, and through a depth D of the silicon substrate, wherein D≧0; forming insulative spacers on sidewalls of the trench; and growing an epitaxial layer of silicon or silicon-germanium alloy in the trench from a bottom of the trench to a height at or above the silicon layer, wherein the insulative spacers provide electrical insulation between the silicon layer outside the trench and the epitaxial layer.
Claim 3
Dependent Claim 52 words
The method of claim 1 , wherein the height is above the silicon layer, and further comprising removing a portion of the epitaxial layer that is above the silicon layer, resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.
Claim 4
Dependent Claim 21 words
The method of claim 2 , wherein removing the portion of the epitaxial layer is accomplished by chemical mechanical polishing (CMP).
Claim 5
Dependent Claim 34 words
The method of claim 2 , wherein removing the portion of the epitaxial layer includes: thermally oxidizing the portion of the epitaxial layer; and etching away the thermally oxidized portion of the epitaxial layer.
Claim 6
Dependent Claim 75 words
The method of claim 1 , further comprising after the step of forming a SOI structure and before the anisotropically etching step, forming a pad layer on the silicon layer; wherein the anisotropically etching step further comprises etching through the pad layer so that the trench passes through the pad layer; and wherein the step of growing the epitaxial layer further comprises growing the epitaxial layer to a height at or above the pad layer.
Claim 7
Dependent Claim 28 words
The method of claim 5 , wherein forming a pad layer comprises forming a pad oxide on the silicon layer and a pad nitride on the pad oxide.
Claim 8
Dependent Claim 21 words
The method of claim 6 , wherein the pad oxide includes silicon dioxide, and wherein the pad nitride includes silicon nitride.
Claim 9
Dependent Claim 57 words
The method of claim 5 , wherein the height is above the pad layer, and further comprising removing a portion of the epitaxial layer that is above the silicon layer and removing the pad layer, resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer.
Claim 10
Dependent Claim 26 words
The method of claim 8 , wherein removing the portion of the epitaxial layer and removing the pad layer are accomplished by chemical mechanical polishing (CMP).
Claim 11
Dependent Claim 44 words
The method of claim 8 , wherein removing the portion of the epitaxial layer and removing the pad layer includes: thermally oxidizing the portion of the epitaxial layer; etching away the thermally oxidized portion of the epitaxial layer; and etching away the pad layer.
Claim 12
Dependent Claim 12 words
The method of claim 5 , further comprising removing the pad layer.
Claim 13
Dependent Claim 29 words
The method of claim 1 , wherein the step of growing an epitaxial layer includes growing an epitaxial layer of single-crystalline silicon by a selective epitaxial silicon deposition process.
Claim 14
Dependent Claim 72 words
The method of claim 1 , wherein the step of growing an epitaxial layer includes growing an epitaxial layer having a single-crystalline silicon region within an interior portion of the trench and a polycrystalline silicon region abutting the trench sidewalls, wherein the polycrystalline silicon region is disposed between the trench sidewalls and the single-crystalline silicon region, and wherein the growing of the epitaxial layer is by a blanket epitaxial silicon deposition process.
Claim 15
Dependent Claim 31 words
The method of claim 1 , wherein the step of growing an epitaxial layer includes growing an epitaxial layer of single-crystalline silicon-germanium alloy by a selective silicon-germanium alloy epitaxial deposition process.
Claim 16
Dependent Claim 77 words
The method of claim 1 , wherein the step of growing an epitaxial layer includes growing an epitaxial layer having a single-crystalline silicon-germanium alloy region within an interior portion of the trench and a polycrystalline silicon-germanium alloy region abutting the trench sidewalls, wherein the polycrystalline silicon-germanium alloy region is disposed between the trench sidewalls and the single-crystalline silicon-germanium alloy region, and wherein the growing of the epitaxial layer is by a blanket epitaxial silicon-germanium alloy deposition process.
Claim 17
Dependent Claim 15 words
The method of claim 1 , further comprising forming an electronic device in the trench.
Claim 18
Dependent Claim 30 words
The method of claim 16 , wherein the step of forming an electronic device in the trench includes forming in the trench an embedded Dynamic Random Access Memory (DRAM) cell.
Claim 19
Dependent Claim 21 words
The method of claim 17 , further comprising forming a field effect transistor coupled to the SOI structure outside the trench.
Claim 20
Dependent Claim 36 words
The method of claim 16 , wherein the step of forming an electronic device in the trench includes forming in the trench a Complementary Metal Oxide Semiconductor (CMOS) circuit which is sensitive to floating body effects.
Claim 21
Dependent Claim 28 words
The method of claim 16 , wherein the step of forming an electronic device in the trench includes forming in the trench a device requiring threshold voltage matching.
Claim 22
Dependent Claim 20 words
The method of claim 16 , further comprising forming a semiconductor device coupled to the SOI structure outside the trench.
Claim 23
Dependent Claim 15 words
The method of claim 21 , wherein the semiconductor device includes a field effect transistor.
Claim 24
Dependent Claim 79 words
The method of claim 1 , wherein D>0, and further comprising: after the step of forming insulative spacers and before the step of growing an epitaxial layer, patterning for forming a subcollector region below the trench, and implanting dopant into the trench resulting in formation of the subcollector region in accordance with the patterning; and after the growing step, forming a bipolar transistor in the trench, wherein a collector of the bipolar transistor is coupled to the subcollector region.
Claim 25
Dependent Claim 23 words
The method of claim 23 , wherein a base of the bipolar transistor is not above a top surface of the silicon layer.
Claim 26
Dependent Claim 22 words
The method of claim 23 , wherein a base of the bipolar transistor is above a top surface of the silicon layer.
Claim 27
Dependent Claim 20 words
The method of claim 23 , further comprising forming a semiconductor device coupled to the SOI structure outside the trench.
Claim 28
Dependent Claim 15 words
The method of claim 26 , wherein the semiconductor device includes a field effect transistor.

References Cited (Backward Citations)

US5366923A Cited
US5504027A Cited
US5481126A Cited
US6287930B1 Cited
US6429099B1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2006-10-20 2007-04-21 2007-10-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2010-10-20 2011-04-21 2011-10-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2014-10-20 2015-04-21 2015-10-21 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag