US6632729B1
Expired / Lapsed
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Laser thermal annealing of high-k gate oxide layers
Assignee: Advanced Micro Devices Inc
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Filing: 2002-06-07
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Granted: 2003-10-14
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Expires: 2022-06-07
Abstract
Abstract A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate having a surface; (b) forming a gate oxide layer on at least a portion of the surface and including an interface therewith, the gate oxide layer comprising a high-k dielectric oxide including a plurality of interface traps at the interface; (c) forming a gate electrode layer on at least a portion of the gate oxide layer; and (d) laser thermal annealing the high-k gate oxide layer to de-activate the interface traps without incurring formation of a low-k dielectric oxide layer at the interface.
Inventors
- 👤 Eric N. Paton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:28
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01338; H10D64/691; H10P; H10P34/00; H10P34/40; H10P34/42; H10D64/01342
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
105 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate having a surface; (b) forming a gate oxide layer on at least a portion of said surface of said semiconductor substrate and including an interface therewith, said gate oxide layer comprising a high-k dielectric oxide including a plurality of interface traps at said interface; (c) forming a gate electrode layer on at least a portion of said gate oxide layer; and (d) laser thermal annealing (LTA) said high-k dielectric gate oxide layer to de-activate said interface traps without incurring formation of a low-k dielectric oxide layer at said interface.
Claim 2
Independent Claim
105 words
A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate having a surface; (b) forming a gate oxide layer on at least a portion of said surface of said semiconductor substrate and including an interface therewith, said gate oxide layer comprising a high-k dielectric oxide including a plurality of interface traps at said interface; (c) forming a gate electrode layer on at least a portion of said gate oxide layer; and (d) laser thermal annealing (LTA) said high-k dielectric gate oxide layer to de-activate said interface traps without incurring formation of a low-k dielectric oxide layer at said interface.
Claim 3
Dependent Claim
39 words
The method as in claim 1 , wherein: step (a) comprises providing a single crystal, polycrystalline, or amorphous silicon (Si) substrate, a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (Si—Ge) substrate, or a gallium arsenide (GaAs) substrate.
Claim 4
Dependent Claim
27 words
The method as in claim 1 , wherein: step (b) comprises forming a high-k gate oxide layer having a dielectric constant k of about 5 or greater.
Claim 5
Dependent Claim
28 words
The method as in claim 3 , wherein: step (b) comprises forming a high-k gate oxide layer having a physical thickness from about 40 to about 100 Å.
Claim 6
Dependent Claim
29 words
The method as in claim 3 , wherein: step (b) comprises forming a high-k gate oxide layer having a SiO 2 equivalent thickness of less than about 40 Å.
Claim 7
Dependent Claim
26 words
The method as in claim 3 , wherein: step (b) comprises forming a high-k gate oxide layer comprising at least one metal and an oxygen-containing material.
Claim 8
Dependent Claim
50 words
The method as in claim 6 , wherein: step (b) comprises forming a high-k metal oxide layer comprising at least one metal and oxygen-containing material selected from the group consisting of metal oxides, metal silicates, metal aluminates, metal titanates, metal zirconates, ferroelectric materials, binary metal oxides, and ternary metal oxides.
Claim 9
Dependent Claim
103 words
The method as in claim 7 , wherein: step (b) comprises forming a high-k metal oxide layer comprising at least one material selected from the group consisting of aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, tantalum oxide, tungsten oxide, cerium oxide, yttrium oxide, zirconium silicate, hafnium silicate, hafnium aluminate, lanthanum aluminate, lead titanate, barium titanate, strontium titanate, barium strontium titanate, lead zirconate; ferroelectric oxides, ternary metal oxides, PST (PbSc x Ta 1−x O 3 ), PZN (PbZn x Nb 1−x O 3 ), PZT (PbZr x Ti 1−x O 3 ), and PMN (PbMg x Nb 1−x O 3 ).
Claim 10
Dependent Claim
39 words
The method as in claim 3 , wherein: step (b) comprises forming a high-k gate oxide layer which further includes bulk traps; and step (d) further comprises thermal annealing the high-k gate oxide layer to de-activate said bulk traps.
Claim 11
Dependent Claim
38 words
The method as in claim 1 , wherein: step (c) comprises forming a gate electrode layer comprising at least one electrically conductive material selected from the group consisting of metals, metal silicides, polysilicon, doped polysilicon, and amorphous silicon.
Claim 12
Dependent Claim
33 words
The method as in claim 1 , wherein: step (d) comprises performing thermal annealing without incurring formation of a low-k dielectric oxide layer having a dielectric constant k of about 4 or less.
Claim 13
Dependent Claim
23 words
The method as in claim 11 , wherein: step (d) comprises performing thermal annealing without incurring formation of a low-k silicon oxide layer.
Claim 14
Dependent Claim
92 words
The method as in claim 1 wherein: step (d) comprises performing LTA utilizing a gas immersion laser process with an inert gas atmosphere and a laser wavelength from about 200 nm to about 1.25 μm and irradiation fluence from about 0.10 to about 1 Joule/cm 2 for an interval sufficient to anneal out defects in the gate oxide layer without incurring: (1) formation of a low-k dielectric oxide layer having a dielectric constant k of about 4 or less and (2) melting of the semiconductor substrate material and/or the gate electrode material.
Claim 15
Dependent Claim
61 words
The method as in claim 1 , further comprising the steps of: (e) patterning said gate electrode layer to form a gate electrode having a pre-selected width and a pair of opposing side edges; and (f) forming a pair of lightly-doped (LDD) source/drain extension regions in said semiconductor substrate by dopant ion implantation utilizing said gate electrode as an implantation mask.
Claim 16
Dependent Claim
83 words
The method as in claim 14 , further comprising the steps of: (g) forming insulative sidewall spacers on each of said pair of opposing side edges of said gate electrode; and (h) forming a pair of heavier-doped source/drain regions in said semiconductor substrate by dopant ion implantation utilizing said gate electrode with said insulative sidewall spacers thereon as an implantation mask; wherein step (d) is performed after performing step (h) in order to simultaneously activate the implanted dopant ions in said source/drain regions.
References Cited (Backward Citations)
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