Patent US6613626B1 successfully refreshed from Google Patents.
US6613626B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of forming CMOS transistor having a deep sub-micron mid-gap metal gate
Assignee: Sharp Laboratories of America Inc
•
Filing: 2000-06-27
•
Granted: 2003-09-02
•
Expires: 2020-06-27
Abstract
Abstract A CMOS transistor is formed on a single crystal silicon substrate. Active regions are formed on the substrate, including an nMOST active region and a pMOST active region. An epitaxial layer of undoped silicon is formed over the active regions. Out-diffusion from the underlying active regions produces dopant densities within the epitaxial layer one, or more, orders of magnitude lower than dopant densities within the underlying active regions. In a preferred embodiment, the epitaxial layer is counter doped by implanting ions of the opposite type to those within the underlying active region. Counter doping further reduces the dopant density, to reduce the threshold voltage further.
Inventors
- 👤 Sheng Teng Hsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:14
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/691; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/0172; H10D84/02; H10D84/03; H10D84/038; H10D30/00; H10D30/60
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
85 words
A method of forming a CMOS transistor structure on a silicon substrate, comprising the steps of: a) forming active regions on a silicon substrate by doping with dopants of a predetermined conductivity type to a desired doping level, b) growing a thin epitaxial layer of undoped silicon over each active region such that out-diffusion of the dopants in the underlying active regions dopes the epitaxial layer to adjust the threshold voltage; and c) implanting ions into the epitaxial layer to further control the threshold voltage.
Claim 2
Independent Claim
85 words
A method of forming a CMOS transistor structure on a silicon substrate, comprising the steps of: a) forming active regions on a silicon substrate by doping with dopants of a predetermined conductivity type to a desired doping level, b) growing a thin epitaxial layer of undoped silicon over each active region such that out-diffusion of the dopants in the underlying active regions dopes the epitaxial layer to adjust the threshold voltage; and c) implanting ions into the epitaxial layer to further control the threshold voltage.
Claim 3
Dependent Claim
53 words
The method of claim 1 , wherein the active region is an n-well formed by implanting phosphorous, or arsenic ions in a pMOST region at an energy level of between about 100 keV to 400 keV and at a dose of between about 1.0·10 12 cm −2 to 1.0·10 14 cm −2 .
Claim 4
Dependent Claim
50 words
The method of claim 1 wherein the active region is a p-well formed by implanting boron ions in an nMOST region at an energy level of between about 30 keV to 80 keV and at a dose of between about 1.0·10 12 cm −2 to 1.0·10 14 cm −2 .
Claim 5
Dependent Claim
26 words
The method of claim 1 , wherein the thin epitaxial layer of silicon is grown to a thickness of between about 10 nm to 100 nm.
Claim 6
Dependent Claim
55 words
The method of claim 1 , wherein the step of implanting ions into the epitaxial layer is accomplished by implanting BF 2 ions into the epitaxial layer at an energy level of between about 2 keV and 60 keV at a dose of between about 5.0·10 10 cm −2 and 5.0·10 11 cm −2 .
Claim 7
Dependent Claim
56 words
The method of claim 1 , wherein the step of implanting ions into the epitaxial layer is accomplished by implanting phosphorous, or arsenic, ions into the epitaxial layer at an energy level of between about 1 keV and 50 keV at a dose of between about 5.0·10 10 cm −2 and 5.0·10 11 cm −2 .
Claim 8
Independent Claim
72 words
A method of forming a CMOS transistor structure on a silicon substrate, comprising the steps of: a) forming active regions on a silicon substrate by forming n-well and p-well regions; and b) growing a thin epitaxial layer of undoped silicon over each active region such that out-diffusion of the dopants in the underlying well dopes the epitaxial layer to adjust the threshold voltage, wherein additional ions are implanted into the epitaxial layer.
Claim 9
Independent Claim
72 words
A method of forming a CMOS transistor structure on a silicon substrate, comprising the steps of: a) forming active regions on a silicon substrate by forming n-well and p-well regions; and b) growing a thin epitaxial layer of undoped silicon over each active region such that out-diffusion of the dopants in the underlying well dopes the epitaxial layer to adjust the threshold voltage, wherein additional ions are implanted into the epitaxial layer.
Claim 10
Dependent Claim
51 words
The method of claim 7 , wherein the n-well region is formed by implanting phosphorous, or arsenic, ions in a pMOST region at an energy level of between about 100 keV to 400 keV and at a dose of between about 1.0·10 12 cm −2 to 1.0·10 14 cm −2 .
Claim 11
Dependent Claim
13 words
The method of claim 7 , wherein the additional ions are counter dopants.
Claim 12
Dependent Claim
55 words
The method of claim 9 , wherein the step of implanting ions into the epitaxial layer is accomplished by implanting BF 2 ions into the epitaxial layer at an energy level of between about 2 keV and 60 keV at a dose of between about 5.0·10 10 cm −2 and 5.0·10 11 cm −2 .
Claim 13
Dependent Claim
21 words
The method of claim 7 , wherein the additional ions are of the same conductivity type as the underlying n-well region.
Claim 14
Dependent Claim
56 words
The method of claim 11 , wherein the step of implanting ions into the epitaxial layer is accomplished by implanting phosphorous, or arsenic, ions into the epitaxial layer at an energy level of between about 1 keV and 50 keV at a dose of between about 5.0·10 10 cm −2 and 5.0·10 11 cm −2 .
Claim 15
Dependent Claim
49 words
The method of claim 7 , wherein the p-well region is formed by implanting boron ions in an nMOST region at an energy level of between about 30 keV to 80 keV and at a dose of between about 1.0·10 12 cm −2 to 1.0·10 14 cm −2 .
Claim 16
Dependent Claim
13 words
The method of claim 7 , wherein the additional ions are counter dopants.
Claim 17
Dependent Claim
56 words
The method of claim 14 , wherein the step of implanting ions into the epitaxial layer is accomplished by implanting phosphorous, or arsenic, ions into the epitaxial layer at an energy level of between about 1 keV and 50 keV at a dose of between about 5.0·10 10 cm −2 and 5.0·10 11 cm −2 .
Claim 18
Dependent Claim
21 words
The method of claim 7 , wherein the additional ions are of the same conductivity type as the underlying p-well region.
Claim 19
Dependent Claim
55 words
The method of claim 16 , wherein the step of implanting ions into the epitaxial layer is accomplished by implanting BF 2 ions into the epitaxial layer at an energy level of between about 2 keV and 60 keV at a dose of between about 5.0·10 10 cm −2 and 5.0·10 11 cm −2 .
Claim 20
Independent Claim
142 words
A method of forming a CMOS transistor on a silicon substrate, comprising the steps of: a) depositing a silicon dioxide layer and a silicon nitride layer overlying a silicon substrate; b) isolating active regions by shallow trench isolation; c) etching away the silicon nitride layer to expose the underlying silicon dioxide layer; d) forming an n-well and a p-well within separate active regions by implanting ions; e) removing the silicon dioxide layer; f) growing a thin epitaxial layer of undoped silicon over each active region such that out-diffusion of the dopants in the underlying well dopes the epitaxial layer to adjust the threshold voltage; g) forming a layer of oxide overlying the thin epitaxial layer; h) implanting dopants through the oxide layer into the thin epitaxial layer; i) forming a gate structure, source regions and drain regions; and j) completing the transistor.
Claim 21
Independent Claim
142 words
A method of forming a CMOS transistor on a silicon substrate, comprising the steps of: a) depositing a silicon dioxide layer and a silicon nitride layer overlying a silicon substrate; b) isolating active regions by shallow trench isolation; c) etching away the silicon nitride layer to expose the underlying silicon dioxide layer; d) forming an n-well and a p-well within separate active regions by implanting ions; e) removing the silicon dioxide layer; f) growing a thin epitaxial layer of undoped silicon over each active region such that out-diffusion of the dopants in the underlying well dopes the epitaxial layer to adjust the threshold voltage; g) forming a layer of oxide overlying the thin epitaxial layer; h) implanting dopants through the oxide layer into the thin epitaxial layer; i) forming a gate structure, source regions and drain regions; and j) completing the transistor.
Claim 22
Independent Claim
79 words
A method of forming a CMOS transistor structure on a silicon substrate, comprising the steps of: a) forming active regions on a silicon substrate by forming n-well and p-well regions; and b) growing a thin epitaxial layer of undoped silicon over each active region such that out-diffusion of the dopants in the underlying well dopes the epitaxial layer to adjust the threshold voltage, wherein additional ions are implanted into the epitaxial layer, wherein the additional ions are counter dopants.
Claim 23
Independent Claim
79 words
A method of forming a CMOS transistor structure on a silicon substrate, comprising the steps of: a) forming active regions on a silicon substrate by forming n-well and p-well regions; and b) growing a thin epitaxial layer of undoped silicon over each active region such that out-diffusion of the dopants in the underlying well dopes the epitaxial layer to adjust the threshold voltage, wherein additional ions are implanted into the epitaxial layer, wherein the additional ions are counter dopants.
Claim 24
Dependent Claim
56 words
The method of claim 19 , wherein the step of implanting ions into the epitaxial layer is accomplished by implanting phosphorous, or arsenic, ions into the epitaxial layer at an energy level of between about 1 keV and 50 keV at a dose of between about 5.0·10 10 cm −2 and 5.0·10 11 cm −2 .
Claim 25
Independent Claim
87 words
A method of forming a CMOS transistor structure on a silicon substrate, comprising the steps of: a) forming active regions on a silicon substrate by forming n-well and p-well regions; and b) growing a thin epitaxial layer of undoped silicon over each active region such that out-diffusion of the dopants in the underlying well dopes the epitaxial layer to adjust the threshold voltage, wherein additional ions are implanted into the epitaxial layer, wherein the additional ions are of the same conductivity type as the underlying p-well region.
Claim 26
Independent Claim
87 words
A method of forming a CMOS transistor structure on a silicon substrate, comprising the steps of: a) forming active regions on a silicon substrate by forming n-well and p-well regions; and b) growing a thin epitaxial layer of undoped silicon over each active region such that out-diffusion of the dopants in the underlying well dopes the epitaxial layer to adjust the threshold voltage, wherein additional ions are implanted into the epitaxial layer, wherein the additional ions are of the same conductivity type as the underlying p-well region.
Claim 27
Dependent Claim
55 words
The method of claim 21 , wherein the step of implanting ions into the epitaxial layer is accomplished by implanting BF 2 ions into the epitaxial layer at an energy level of between about 2 keV and 60 keV at a dose of between about 5.0·10 10 cm −2 and 5.0·10 11 cm −2 .
Claim 28
Dependent Claim
18 words
The method of claim 1 , further comprising forming a layer of silicon dioxide prior to implanting ions.
Claim 29
Dependent Claim
19 words
The method of claim 7 , further comprising forming a layer of silicon dioxide prior to implanting additional ions.
References Cited (Backward Citations)
US4966861A
Cited
US4777147A
Cited
US5338697A
Cited
US6190179B1
Cited
US5306667A
Cited
US5668025A
Cited
US5665616A
Cited
US5950082A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-09-01 | 2007-03-03 | 2007-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-09-01 | 2011-03-03 | 2011-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-09-01 | 2015-03-03 | 2015-09-02 | $7700.00 | Window Closed / Lapsed |