Cross-correlation timing calibration for wafer-level IC tester interconnect systems

Claim 1

A method for calibrating TEST signal timing of an integrated circuit (IC) tester having a plurality of probes with tips for contacting input/output (I/O) terminals on a surface of an IC, and having a plurality of tester channels, each tester channel for generating a TEST signal at a tip of a corresponding one of said probes in response to a periodic CLOCK signal with a delay adjustable by drive calibration data supplied as input to the tester channel, the TEST signal including edges occurring in an edge timing pattern selected by programming data provided as input to the tester channel, the method comprising the steps of, for each said tester channel: a. providing the input programming data to the tester channel so that the tester channel responds to the CLOCK signal by generating a TEST signal having a repetitive edge timing pattern at the tester channel's corresponding probe tip, b. supplying the input drive calibration data to the tester channel to adjust said delay with which the tester channel produces said TEST signal in response to the CLOCK signal, c. generating a periodic reference (REF) signal having said repetitive edge timing pattern, and d. cross-correlating the TEST signal generated at step b to said REF signal over a finite time interval to produce cross-correlation data indicating how closely the TEST signal matches the REF signal in phase.

Claim 2

A method for calibrating TEST signal timing of an integrated circuit (IC) tester having a plurality of probes with tips for contacting input/output (I/O) terminals on a surface of an IC, and having a plurality of tester channels, each tester channel for generating a TEST signal at a tip of a corresponding one of said probes in response to a periodic CLOCK signal with a delay adjustable by drive calibration data supplied as input to the tester channel, the TEST signal including edges occurring in an edge timing pattern selected by programming data provided as input to the tester channel, the method comprising the steps of, for each said tester channel: a. providing the input programming data to the tester channel so that the tester channel responds to the CLOCK signal by generating a TEST signal having a repetitive edge timing pattern at the tester channel's corresponding probe tip, b. supplying the input drive calibration data to the tester channel to adjust said delay with which the tester channel produces said TEST signal in response to the CLOCK signal, c. generating a periodic reference (REF) signal having said repetitive edge timing pattern, and d. cross-correlating the TEST signal generated at step b to said REF signal over a finite time interval to produce cross-correlation data indicating how closely the TEST signal matches the REF signal in phase.

Claim 15

A method for calibrating TEST signal timing of an integrated circuit (IC) tester having a plurality of probes with tips for contacting input/output (I/O) terminals on a surface of an IC, and having a plurality of tester channels, each tester channel for generating a TEST signal at a tip of a corresponding one of said probes in response to a periodic CLOCK signal with a delay adjustable by drive calibration data supplied as input to the tester channel, the TEST signal including edges occurring in an edge timing pattern selected by programming data provided as input to the tester channel, the method comprising the steps of, for each said tester channel: a. providing the input programming data to the tester channel so that the tester channel responds to the CLOCK signal by generating a TEST signal having a repetitive edge timing pattern at the tester channel's corresponding probe tip; b. supplying the input drive calibration data to the tester channel to adjust said delay with which the tester channel produces said TEST signal in response to the CLOCK signal; c. generating a periodic reference (REF) signal having said repetitive edge timing pattern; d. generating a MATCH signal having a magnitude indicating how well an amplitude of the periodic TEST signal appearing at the probe tip matches an amplitude of the REF signal; e. integrating the MATCH signal over a finite time interval to produce an analog cross-correlation (CC) signal; f. digitizing the CC signal at an end of the finite time interval to produce the cross-correlation data; g. performing a plurality of iterations of steps b-f, providing the tester channel with differing values of the input drive calibration data during each iteration of step b; h. determining a particular iteration of steps b-f for which cross-correlation data produced at step f indicates the channel's TEST signal most closely matched the REF signal in phase; and i. calibrating timing of the tester channel by providing input drive calibration data to said tester channel of value matching a that of input drive calibration data provided to said tester channel during said particular iteration of steps b-f determined at step h.

Claim 16

A method for calibrating TEST signal timing of an integrated circuit (IC) tester having a plurality of probes with tips for contacting input/output (I/O) terminals on a surface of an IC, and having a plurality of tester channels, each tester channel for generating a TEST signal at a tip of a corresponding one of said probes in response to a periodic CLOCK signal with a delay adjustable by drive calibration data supplied as input to the tester channel, the TEST signal including edges occurring in an edge timing pattern selected by programming data provided as input to the tester channel, the method comprising the steps of, for each said tester channel: a. providing the input programming data to the tester channel so that the tester channel responds to the CLOCK signal by generating a TEST signal having a repetitive edge timing pattern at the tester channel's corresponding probe tip; b. supplying the input drive calibration data to the tester channel to adjust said delay with which the tester channel produces said TEST signal in response to the CLOCK signal; c. generating a periodic reference (REF) signal having said repetitive edge timing pattern; d. generating a MATCH signal having a magnitude indicating how well an amplitude of the periodic TEST signal appearing at the probe tip matches an amplitude of the REF signal; e. integrating the MATCH signal over a finite time interval to produce an analog cross-correlation (CC) signal; f. digitizing the CC signal at an end of the finite time interval to produce the cross-correlation data; g. performing a plurality of iterations of steps b-f, providing the tester channel with differing values of the input drive calibration data during each iteration of step b; h. determining a particular iteration of steps b-f for which cross-correlation data produced at step f indicates the channel's TEST signal most closely matched the REF signal in phase; and i. calibrating timing of the tester channel by providing input drive calibration data to said tester channel of value matching a that of input drive calibration data provided to said tester channel during said particular iteration of steps b-f determined at step h.

Claim 20

An apparatus for testing an integrated circuit (IC) having a plurality of input/output (I/O) terminals, the apparatus comprising: means for generating a periodic CLOCK signal; a plurality of probes with tips, each for contacting a separate I/O terminal of said IC a plurality of tester channels, each tester channel for generating a TEST signal at a tip of a corresponding one of said probes in response to a periodic CLOCK signal with a delay adjustable by drive calibration data supplied as input to the tester channel, the TEST signal including edges occurring in an edge timing pattern selected by programming data provided as input to the tester channel; means for generating a reference (REF) signal having a repetitive edge timing pattern; and cross-correlation means for cross-correlating the TEST signal generated at each probe tip to said REF signal over a finite time interval to produce cross-correlation data indicating how closely the TEST signal matches the REF signal in phase.

Claim 21

An apparatus for testing an integrated circuit (IC) having a plurality of input/output (I/O) terminals, the apparatus comprising: means for generating a periodic CLOCK signal; a plurality of probes with tips, each for contacting a separate I/O terminal of said IC a plurality of tester channels, each tester channel for generating a TEST signal at a tip of a corresponding one of said probes in response to a periodic CLOCK signal with a delay adjustable by drive calibration data supplied as input to the tester channel, the TEST signal including edges occurring in an edge timing pattern selected by programming data provided as input to the tester channel; means for generating a reference (REF) signal having a repetitive edge timing pattern; and cross-correlation means for cross-correlating the TEST signal generated at each probe tip to said REF signal over a finite time interval to produce cross-correlation data indicating how closely the TEST signal matches the REF signal in phase.