Method for calibrating variable delay circuit and a variable delay circuit using the same

Claim 3

The method of claim 1, wherein said step (s) includes a step of prewriting a fixed value greater than said nominal delay step d s , as an initial value in the column of error of said calibration table.

Claim 4

The method of claim 1 or 2, wherein, if the delay time t d0 between the input and output of said variable delay circuit, when supplied with a control signal CC 0 for bypassing all of said delay stages, is taken as an offset delay, said step (b) includes a step of measuring the delay time t d1 between the input and output of said variable delay circuit for each of said control signal values CC i and obtaining said amount of delay D i as given by the following equation: D.sub.i =t.sub.d1 -t.sub.d0.

Claim 5

The method of claim 1 or 2, wherein an m-th (m=1, 2, . . . , M) one of said delay stages is weighted about 2 m-1 .

Claim 6

A variable delay circuit which generates a delay calibrated by a control signal value in correspondence with a nominal amount of delay D sk for each nominal minimum delay step d s , said variable delay circuit comprising: M delay stages of differently weighted amounts of delay; M multiplexers connected to the outputs of said M delay stages, respectively, for selectively outputting inputs to and outputs from said delay stages, said M delay stages and said M multiplexers being connected in cascade; control signal converting means responsive to a control signal fed thereto, for generating desired control signal values from O to K and applying them to said multiplexers to set in said M delay stages desired amounts of delay corresponding to nominal amounts of delay D sk =d s k (k=0, 1, 2, . . . , K) for each nominal minimum delay step, said M and K being integers equal to or greater than 2; delay time measuring means for measuring the delay time between the input and output of said variable delay circuit upon each change of said control signal values from O to K; a memory having defined therein an at least K-row calibration table with columns for prestoring an error and a control signal value which provides said error; and calculating means for: dividing an amount of delay D i measured for each given control signal value CC i by the minimum nominal delay step d s of a variable delay circuit; calculating first and second errors, R k =D i -d s k and R k+1 =d s -R k , between the value k of an integral part of the resulting quotient and two adjoining nominal amounts of delay D sk and D sk+1 ; making a check to determine if the first error R k is smaller than an error held in a k-th row of a calibration table in correspondence with a nominal set signal value CS=k; if so, writing the first error R k and the corresponding control signal value CC i over the existing values in the column of the k-th row of the calibration table; making a check to determine if the second error R k+1 is smaller than an error held in a (k+1)-th row of the calibration table in correspondence with a nominal setting signal value CS=k+1; if so, writing the second error R k+1 and the corresponding control signal value CC i over the existing values in the column of the (k+1)-th row of the calibration table; and repeatedly executing these operations for i=0 to i=2 M -1, whereby control signal values, which minimize errors between delay times of the variable delay circuit and the nominal amounts of delay, are generated in O-th to K-th rows of the calibration table in correspondence with the respective nominal setting signal values CS.

Claim 7

A variable delay circuit which generates a delay calibrated by a control signal value in correspondence with a nominal amount of delay D sk for each nominal minimum delay step d s , said variable delay circuit comprising: M delay stages of differently weighted amounts of delay; M multiplexers connected to the outputs of said M delay stages, respectively, for selectively outputting inputs to and outputs from said delay stages, said M delay stages and said M multiplexers being connected in cascade; control signal converting means responsive to a control signal fed thereto, for generating desired control signal values from O to K and applying them to said multiplexers to set in said M delay stages desired amounts of delay corresponding to nominal amounts of delay D sk =d s k (k=0, 1, 2, . . . , K) for each nominal minimum delay step, said M and K being integers equal to or greater than 2; delay time measuring means for measuring the delay time between the input and output of said variable delay circuit upon each change of said control signal values from O to K; a memory having defined therein an at least K-row calibration table with columns for prestoring an error and a control signal value which provides said error; and calculating means for: dividing an amount of delay D i measured for each given control signal value CC i by the minimum nominal delay step d s of a variable delay circuit; calculating first and second errors, R k =D i -d s k and R k+1 =d s -R k , between the value k of an integral part of the resulting quotient and two adjoining nominal amounts of delay D sk and D sk+1 ; making a check to determine if the first error R k is smaller than an error held in a k-th row of a calibration table in correspondence with a nominal set signal value CS=k; if so, writing the first error R k and the corresponding control signal value CC i over the existing values in the column of the k-th row of the calibration table; making a check to determine if the second error R k+1 is smaller than an error held in a (k+1)-th row of the calibration table in correspondence with a nominal setting signal value CS=k+1; if so, writing the second error R k+1 and the corresponding control signal value CC i over the existing values in the column of the (k+1)-th row of the calibration table; and repeatedly executing these operations for i=0 to i=2 M -1, whereby control signal values, which minimize errors between delay times of the variable delay circuit and the nominal amounts of delay, are generated in O-th to K-th rows of the calibration table in correspondence with the respective nominal setting signal values CS.

Claim 8

The variable delay circuit of claim 5, wherein there is prestored, as an initial value, a fixed value greater than said nominal delay step d s in the column of error of said calibration table in said memory.

Claim 9

The variable delay circuit of claim 5 or 6, wherein , if the delay time t d0 between the input and output of said variable delay circuit, when supplied with a control signal CC 0 for bypassing all of said delay stages, is taken as an offset delay, said delay time measuring means measures the delay time t d1 between the input and output of said variable delay circuit for each of said control signal values CC i and said calculating means obtains said amount of delay D i as given by the following equation: D.sub.i =t.sub.d1 -t.sub.d0.

Claim 10

The variable delay circuit of claim 5 or 6, wherein an m-th (m=1, 2, . . . , M) one of said delay stages is weighted about 2 m-1 .