All digital on-the-fly time delay calibrator

Claim 1

A circuit in a semiconductor integrated circuit for providing a signal which is accurately representative of propagation delay in circuits in said integrated circuit comprising: an input terminal, said input terminal for receiving a clock reference signal; a serially connected chain of unit delay cells including a first unit delay cell, said first unit delay cell being connected to said input terminal to launch said clock reference signal for propagation down said chain of unit delay cells, each cell having an input and output; a plurality of taps, each tap being connected to a said unit delay cell, said tap providing a signal representative of said unit delay cell output; a phase comparator array, said phase comparator array including a plurality of logic gates, where each said tap has a logic gate corresponding to said tap, and each said corresponding logic gate having a first input connected to said input terminal for receiving said clock reference and a second input connected to said corresponding tap, each said logic gate having an output signal; circuit means to periodically simultaneously sample and hold a binary representation of the output value of each said output signal of each said logic gate output, wherein said sample and hold circuit means has substantially identical threshold response to falling signals and to rising signals so that a threshold change which lowers the sensitivity to a transition of said output signal of a said logic gate from a one to a zero will have a matching decrease in the sensitivity to a transition of said output signal of a said logic gate from a zero to a one so that the time of occurrence of the midpoint between a falling/rising signal transition time and the next rising/failing signal transition time is substantially unchanged as a function of threshold changes; means to analyze said output signals of each said logic gate to determine the address of the tap where said logic gate output goes from 1 to 0 being the window low address, and the address of said tap where said logic gate output goes from 0 to 1 being the window high address; and means to determine the address of the tap at which the phase of said propagating clock reference signal, in operation, is closest to being exactly in phase with said clock reference signal applied to said input terminal, said tap being called the zero tap, said means to determine the address of said zero tap being coupled to said means to analyze said output signals of each said logic gate, said means to determine the address of said zero tap including means for providing an output signal representative of said address of said zero phase tap which said output signals is accurately representative of propagation delay in circuits in said integrated circuit.