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EP0919823A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

System for verifying signal timing accuracy on a digital testing device

Assignee: Agilent Technologies Inc
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Filing: 1998-09-14
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Granted: —
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Expires: 2018-09-14
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Abstract

Abstract An apparatus and method are provided for testing component tolerances of a device (100) for testing integrated circuits. The testing device (100) is generally characterized by a plurality of test connectors disposed at a test head (205), wherein each test connector carries electrical signals for a test channel. Further, each test channel generally corresponds to a circuit board (400) that includes at least one driver (402) and one receiver (404). In this general type of tester (100), a system is provided that includes a specialized DUT board (500) that establishes a low impedance electrical connection ( i.e., short) between electrical conductors (506) of a first and second test connector. Through this low impedance path, a first driver (402a) from a first circuit board (400a) is directly connected ( i.e., shorted) to a first receiver (404b) on a second circuit board (400b). A controller (206) is configured to control the first driver (402a) to output an electrical signal at a predetermined time. The preferred embodiment further includes evaluating mechanism (206, 812) designed to detect the signal received at the first receiver (404b), and timing mechanism (206, 810) configured to time the signal delay. Specifically, the timing mechanism (206, 810) is configured to determine the length of time required to propagate the signal from the driver (402) to the receiver (404). In accordance with the method aspect, the method includes the step of establishing an electrical connection between electrical conductors (506) of a first and second test connector such that a first driver (402a) from a first circuit board (400a) is electrically connected across a low impedance path to a first receiver (404b) on a second circuit board (400b). The method then controls the output of the first driver (402a) to drive an edge of an electrical signal at a predetermined time and detecting the signal received at the first receiver (404b). Finally, the method determines whether the signal received at the first receiver (404b) is within a predetermined time period of the predetermined signal level output from the first driver (402a).

Inventors

  • 👤 William R. Lawrence
  • 👤 David H. Armstrong

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-26 21:28
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31908; G01R31/3191

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 187 words
An apparatus for testing component tolerance of a device (100) for testing integrated circuits, the device (100) having a plurality of test connectors disposed at a test head, each test connector having electrical conductors (506) carrying electrical signals for a test channel, wherein each test channel corresponds to a circuit board (400) that includes at least one driver (402) and one receiver (404), the system comprising: shorting means (500) for establishing a low impedance electrical connection between electrical conductors of a first and second test connector, such that a first driver (402a) from a first circuit board (400a) is electrically connected across a low impedance path to a first receiver (404b) on a second circuit board (400b); a controller (206) configured to control the first driver (402a) to output an electrical signal at a predetermined time; evaluating means (206, 812) designed to detect the signal received at the first receiver (404b); and timing means (206, 810) configured to time a signal delay from the time that the first driver (402a) outputs an electrical signal to the time that the evaluating means (206, 812) detects the received signal.
Claim 2
Dependent Claim 39 words
The apparatus as defined in claim 1, wherein the shorting means (500) includes a printed circuit board containing metal layers that establish direct conductive paths between pins on the first test connector to pins on the second test connector.
Claim 3
Dependent Claim 31 words
The apparatus as defined in claim 1, wherein the evaluating means (500) and the timing means (206, 810) are realized through program code that controls the operation of a processing unit.
Claim 4
Dependent Claim 43 words
The apparatus as defined in claim 3, wherein the processing unit is a device selected from the group consisting of: a microprocessor, a microcontroller, an embedded controller, an application specific integrated circuit, and dedicated hardware specially designed to carry-out processing and control functions.
Claim 5
Dependent Claim 43 words
The apparatus as defined in claim 1, wherein the controller (206) is configured output the electrical signal coincident with one of a plurality of edges, which plurality of edges are periodically disposed within a period of a master clock cycle of the apparatus.
Claim 6
Dependent Claim 41 words
The apparatus as defined in claim 1, wherein the timing means (206, 810) is configured to measure the time when a signal arrives at the interface between a device under test (DUT) board and the tester (100) within a tester cycle.
Claim 7
Dependent Claim 36 words
The apparatus as defined in claim 1, further including means (206) for performing a statistical analysis of timing test results, wherein the timing test results are generated from executing a timing test a plurality of times.
Claim 8
Dependent Claim 166 words
In a testing device for testing integrated circuits having a plurality of test connectors disposed at a test head, each test connector having electrical conductors carrying electrical signals for a test channel, wherein each test channel corresponds to a circuit board (400) that includes at least one driver (402) and one receiver (404), a method for diagnosing component timing variances comprising the steps of: establishing an electrical connection between electrical conductors (506) of a first and second test connector such that a first driver (402a) from a first circuit board (400a) is electrically connected across a low impedance path to a first receiver (404b) on a second circuit board (400b); controlling the output of the first driver to drive an edge of an electrical signal at a predetermined time; detecting the signal received at the first receiver (404b); and determining that the signal received at the first receiver (404b) is within a predetermined time period of the predetermined signal level output from the first driver (402a).
Claim 9
Dependent Claim 111 words
The method as defined in claim 8, further including the steps of: establishing an electrical connection between electrical conductors (506) of a first and second test connector such that a second driver (402b) from a second circuit board (400b) is electrically connected across a low impedance path to a second receiver (404a) on a first circuit board (400a); controlling the output of the second driver (402b) to drive an electrical signal at a predetermined time; detecting the signal received at the second receiver (404a); and determining that the signal received at the second receiver (404a) is within a predetermined time period of the predetermined signal output from the second driver (402b).
Claim 10
Dependent Claim 79 words
The method as defined in claim 8, wherein the step of establishing an electrical connection further comprises establishing an electrical connection between electrical conductors (506) of a first and second test connector such that a plurality of drivers (402a) from a first circuit board (400a) are electrically connected across low impedance paths to a plurality of receivers (404b) on a second circuit board (400b), wherein each of the plurality of drivers is known to be within a specified tolerance.

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