Patent US6583512B2 successfully refreshed from Google Patents.
US6583512B2
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Semiconductor device and method for fabricating the same
Assignee: Nuvoton Technology Corp Japan
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Filing: 2001-10-01
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Granted: 2003-06-24
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Expires: 2021-10-01
Abstract
Abstract In a semiconductor device functioning as a three-dimensional device composed of two semiconductor chips bonded to each other, the back surface of the upper semiconductor chip is polished, the entire side surfaces of the upper semiconductor chip are covered with a resin layer, or the center portion of the upper semiconductor chip is formed to be thicker than the peripheral portion thereof. This suppresses the occurrence of a package crack and improves the reliability of the semiconductor device.
Inventors
- 👤 Yukiko Nakaoka
- 👤 Kazuhiko Matsumura
- 👤 Hideyuki Kaneko
- 👤 Koichi Nagao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:08
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/01; H10W74/014; H10D; H10D62/00; H10D62/10; H10D62/117; H10W72/00; H10W72/01; H10W72/0198; H10W74/012; H10W74/10; H10W74/111; H10W74/129; H10W74/15; H10W90/00; H10W72/071; H10W72/072; H10W72/07231; H10W72/07232; H10W72/07236; H10W72/073; H10W72/07331; H10W72/07337; H10W72/07338; H10W72/074; H10W72/075; H10W72/20; H10W72/241; H10W72/251; H10W72/252; H10W72/30; H10W72/321; H10W72/325; H10W72/351; H10W72/352; H10W72/353; H10W72/354; H10W72/381; H10W72/387; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/851; H10W72/853; H10W72/856; H10W72/859; H10W72/874; H10W72/884; H10W72/90; H10W72/921; H10W72/923; H10W72/951; H10W72/952; H10W74/131; H10W74/142; H10W90/20; H10W90/291; H10W90/701; H10W90/721; H10W90/722; H10W90/731; H10W90/732; H10W90/736; H10W90/751; H10W90/754; H10W90/756; Y; Y10; Y10S; Y10S438/00; Y10S438/959; Y10S438/978
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
78 words
A semiconductor device comprising: a first semiconductor chip having a first electrode disposed on an upper surface thereof; and a second semiconductor chip having a second electrode disposed on an upper surface thereof, the second semiconductor chip being mounted on the first semiconductor chip with the second electrode being electrically connected to the first electrode, a corner of a lower surface of the second semiconductor chip being blunted by processing, and an upper surface thereof is substantially plane.
Claim 2
Dependent Claim
78 words
A semiconductor device comprising: a first semiconductor chip having a first electrode disposed on an upper surface thereof; and a second semiconductor chip having a second electrode disposed on an upper surface thereof, the second semiconductor chip being mounted on the first semiconductor chip with the second electrode being electrically connected to the first electrode, a corner of a lower surface of the second semiconductor chip being blunted by processing, and an upper surface thereof is substantially plane.
Claim 3
Dependent Claim
23 words
The semiconductor device of claim 1 , wherein the corner of the lower surface of the second semiconductor chip has a curved surface.
Claim 4
Dependent Claim
32 words
The semiconductor device of claim 2 , wherein the curved surface of the corner of the lower surface of the second semiconductor chip has a radius of curvature larger than 1 μm.
Claim 5
Dependent Claim
20 words
The semiconductor device of claim 1 , wherein a resin layer is interposed between the first and second semiconductor chips.
Claim 6
Dependent Claim
77 words
A semiconductor device comprising: a first semiconductor chip having a first electrode disposed on an upper surface thereof; and a second semiconductor chip having a second electrode disposed on an upper surface thereof, the second semiconductor chip being mounted on the first semiconductor chip with the second electrode being electrically connected to the first electrode, the second semiconductor chip having a center portion thicker than a peripheral portion thereof, and an upper surface thereof is substantially plane.
Claim 7
Dependent Claim
77 words
A semiconductor device comprising: a first semiconductor chip having a first electrode disposed on an upper surface thereof; and a second semiconductor chip having a second electrode disposed on an upper surface thereof, the second semiconductor chip being mounted on the first semiconductor chip with the second electrode being electrically connected to the first electrode, the second semiconductor chip having a center portion thicker than a peripheral portion thereof, and an upper surface thereof is substantially plane.
Claim 8
Dependent Claim
20 words
The semiconductor device of claim 5 , further comprising: a resin layer interposed between the first and second semiconductor chips.
Claim 9
Dependent Claim
19 words
The semiconductor device of claim 6 , wherein the first and second semiconductor chips are sealed with a resin.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
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| 3.5 Years (Year 4) | 2006-06-23 | 2006-12-23 | 2007-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-06-23 | 2010-12-23 | 2011-06-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-06-23 | 2014-12-23 | 2015-06-24 | $7700.00 | Window Closed / Lapsed |