Patent US2058749A successfully refreshed from Google Patents.
Patent US6583000B1 successfully refreshed from Google Patents.
US6583000B1
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Process integration of Si1-xGex CMOS with Si1-xGex relaxation after STI formation
Assignee: Sharp Laboratories of America Inc
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Filing: 2002-02-07
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Granted: 2003-06-24
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Expires: 2022-02-07
Abstract
Abstract A method of forming a CMOS device includes preparing a silicon substrate, including forming plural device regions on the substrate; epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40%; forming a silicon cap layer epitaxially on the SiGe layer; depositing a gate oxide layer; depositing a first polysilicon layer; implanting H+ ions to a depth below the SiGe layer; forming a trench by shallow trench isolation which extends into the substrate; annealing the structure at a temperature of between about 700° C. to 900° C. for between about five minutes to sixty minutes; depositing an oxide layer and a second polysilicon layer, thereby filling the trench; planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench; and completing the CMOS device.
Inventors
- 👤 Sheng Teng Hsu
- 👤 Jong-Jan Lee
- 👤 Jer-shen Maa
- 👤 Douglas James Tweet
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:54
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/0188; H10D84/02; H10D84/03; H10D84/038; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/10; H10W10/17
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
154 words
A method of forming a CMOS device, comprising: preparing a silicon substrate, including forming plural device regions on the substrate; epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40%; forming a silicon cap layer epitaxially on the SiGe layer; depositing a gate oxide layer; depositing a first polysilicon layer; implanting H+ ions to a depth below a SiGe:silicon interface; forming a trench by shallow trench isolation which extends into the substrate; annealing the structure at a temperature of between about 700° C. to 900° C. for between about five minutes to sixty minutes to relax the strained SiGe layer; depositing an oxide layer and a second polysilicon layer, thereby filling the trench; planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench; and completing the CMOS device.
Claim 2
Independent Claim
154 words
A method of forming a CMOS device, comprising: preparing a silicon substrate, including forming plural device regions on the substrate; epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40%; forming a silicon cap layer epitaxially on the SiGe layer; depositing a gate oxide layer; depositing a first polysilicon layer; implanting H+ ions to a depth below a SiGe:silicon interface; forming a trench by shallow trench isolation which extends into the substrate; annealing the structure at a temperature of between about 700° C. to 900° C. for between about five minutes to sixty minutes to relax the strained SiGe layer; depositing an oxide layer and a second polysilicon layer, thereby filling the trench; planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench; and completing the CMOS device.
Claim 3
Dependent Claim
21 words
The method of claim 1 wherein said preparing a substrate includes forming an N-well and a P-well in each device region.
Claim 4
Dependent Claim
83 words
The method of claim 2 wherein said forming an N-well and a P-well in each device region includes implanting phosphorus ions to form the N-well at a dose of about 2·10 13 cm −2 to 5·10 14 cm −2 , at an energy level of 40 keV to 200 keV, and implanting boron ions to from the P-well at a dose of about 2·10 13 cm −2 to 5·10 14 cm −2 , at an energy level of 20 keV to 80 keV.
Claim 5
Dependent Claim
31 words
The method of claim 1 wherein said epitaxially forming a strained SiGe layer includes depositing a layer of strained SiGe to a thickness of between about 2500 Å to 4000 Å.
Claim 6
Dependent Claim
29 words
The method of claim 1 wherein said forming a cap silicon layer includes forming a cap silicon layer to a thickness of between about 50 Å to 300 Å.
Claim 7
Dependent Claim
14 words
The method of claim 1 wherein said forming a trench is a single-step etch.
Claim 8
Dependent Claim
30 words
The method of claim 1 wherein said forming a trench is a two-step etch which includes etching the first polysilicon layer and then etching the underlying layers into the substrate.
Claim 9
Dependent Claim
30 words
The method of claim 1 wherein said implanting H+ ions includes implanting H+ ions to a projected depth of between about 2 nm to 100 nm below the SiGe:silicon interface.
Claim 10
Dependent Claim
42 words
The method of claim 8 wherein said implanting H+ ions includes implanting H+ ions at a dose of between about 1×10 16 cm −2 to 4×10 16 cm −2 , and at an energy of between about 40 keV to 80 keV.
Claim 11
Independent Claim
212 words
A method of forming a CMOS device, comprising: preparing a silicon substrate, including forming plural device regions on the substrate; epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40% and a thickness of between about 2500 Å to 4000 Å, and which forms a SiGe:silicon interface with the silicon substrate; forming a silicon cap layer epitaxially on the SiGe layer; depositing a gate oxide layer; depositing a first polysilicon layer to a thickness of between about 1000 Å and 3000 Å; implanting H+ ions to a depth below the SiGe:silicon interface; forming a trench by shallow trench isolation which extends into the substrate; annealing the structure at a temperature of between about 700° C. to 900° C. for between about five minutes to sixty minutes, wherein said annealing also provides for liner oxidation of the trench sidewall; depositing an oxide layer and a second polysilicon layer, thereby filling the trench; planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench; and completing the CMOS device, including LDD, halo, source/drain ion implantation, gate spacer formation, interlayer dielectric deposition, contact masking and etching, and metalization of electrodes.
Claim 12
Independent Claim
212 words
A method of forming a CMOS device, comprising: preparing a silicon substrate, including forming plural device regions on the substrate; epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40% and a thickness of between about 2500 Å to 4000 Å, and which forms a SiGe:silicon interface with the silicon substrate; forming a silicon cap layer epitaxially on the SiGe layer; depositing a gate oxide layer; depositing a first polysilicon layer to a thickness of between about 1000 Å and 3000 Å; implanting H+ ions to a depth below the SiGe:silicon interface; forming a trench by shallow trench isolation which extends into the substrate; annealing the structure at a temperature of between about 700° C. to 900° C. for between about five minutes to sixty minutes, wherein said annealing also provides for liner oxidation of the trench sidewall; depositing an oxide layer and a second polysilicon layer, thereby filling the trench; planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench; and completing the CMOS device, including LDD, halo, source/drain ion implantation, gate spacer formation, interlayer dielectric deposition, contact masking and etching, and metalization of electrodes.
Claim 13
Dependent Claim
21 words
The method of claim 10 wherein said preparing a substrate includes forming an N-well and a P-well in each device region.
Claim 14
Dependent Claim
83 words
The method of claim 11 wherein said forming an N-well and a P-well in each device region includes implanting phosphorus ions to form the N-well at a dose of about 2·10 13 cm −2 to 5·10 14 cm −2 , at an energy level of 40 keV to 200 keV, and implanting boron ions to from the P-well at a dose of about 2·10 13 cm −2 to 5·10 14 cm −2 , at an energy level of 20 keV to 80 keV.
Claim 15
Dependent Claim
29 words
The method of claim 10 wherein said forming a cap silicon layer includes forming a cap silicon layer to a thickness of between about 50 Å to 300 Å.
Claim 16
Dependent Claim
29 words
The method of claim 10 wherein said implanting H+ ions includes implanting H+ ions to a projected depth of between about 2 nm 100 nm below the SiGe:silicon interface.
Claim 17
Dependent Claim
42 words
The method of claim 14 wherein said implanting H+ ions includes implanting H+ ions at a dose of between about 1×10 16 cm −2 to 4×10 16 cm −2 , and at an energy of between about 40 keV to 80 keV.
Claim 18
Dependent Claim
14 words
The method of claim 10 wherein said forming a trench is a single-step etch.
Claim 19
Dependent Claim
30 words
The method of claim 10 wherein said forming a trench is a two-step etch which includes etching the first polysilicon layer and then etching the underlying layers into the substrate.
Claim 20
Independent Claim
228 words
A method of forming a CMOS device, comprising: preparing a silicon substrate, including forming plural device regions on the substrate and includes an N-well and a P-well in each device region; epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40% and a thickness of between about 2500 Å to 4000 Å; forming a silicon cap layer epitaxially on the SiGe layer to a thickness of between about 50 Å to 300 Å; depositing a gate oxide layer to a thickness of between about 10 Å and 60 Å; depositing a first polysilicon layer; implanting H+ ions to a depth of between about 2 nm to 100 nm below the SiGe layer at a dose of between about 1×10 16 cm −2 to 4×10 16 cm −2 , and at an energy of between about 40 keV to 80 keV; forming a trench by shallow trench isolation which extends into the substrate; annealing the structure at a temperature of between about 700° C. to 900° C. for between about five minutes to sixty minutes; depositing an oxide layer and a second polysilicon layer, thereby filling the trench; planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench; and completing the CMOS device.
Claim 21
Independent Claim
228 words
A method of forming a CMOS device, comprising: preparing a silicon substrate, including forming plural device regions on the substrate and includes an N-well and a P-well in each device region; epitaxially forming a strained SiGe layer on the substrate, wherein the SiGe layer has a germanium content of between about 20% and 40% and a thickness of between about 2500 Å to 4000 Å; forming a silicon cap layer epitaxially on the SiGe layer to a thickness of between about 50 Å to 300 Å; depositing a gate oxide layer to a thickness of between about 10 Å and 60 Å; depositing a first polysilicon layer; implanting H+ ions to a depth of between about 2 nm to 100 nm below the SiGe layer at a dose of between about 1×10 16 cm −2 to 4×10 16 cm −2 , and at an energy of between about 40 keV to 80 keV; forming a trench by shallow trench isolation which extends into the substrate; annealing the structure at a temperature of between about 700° C. to 900° C. for between about five minutes to sixty minutes; depositing an oxide layer and a second polysilicon layer, thereby filling the trench; planarizing the structure to the top of the level of the portion of the second polysilicon layer which is located in the trench; and completing the CMOS device.
Claim 22
Dependent Claim
83 words
The method of claim 18 wherein said forming an N-well and a P-well in each device region includes implanting phosphorus ions to form the N-well at a dose of about 2·10 13 cm −2 to 5·10 14 cm −2 , at an energy level of 40 keV to 200 keV, and implanting boron ions to from the P-well at a dose of about 2·10 13 cm −2 to 5·10 14 cm −2 , at an energy level of 20 keV to 80 keV.
Claim 23
Dependent Claim
14 words
The method of claim 18 wherein said forming a trench is a single-step etch.
Claim 24
Dependent Claim
30 words
The method of claim 18 wherein said forming a trench is a two-step etch which includes etching the first polysilicon layer and then etching the underlying layers into the substrate.
References Cited (Backward Citations)
US4994866A
Cited
US5891769A
Cited
US6464780B1
Cited
US6313016B1
Cited
US20020185686A1
Cited
US6515335B1
Cited
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| 3.5 Years (Year 4) | 2006-06-23 | 2006-12-23 | 2007-06-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-06-23 | 2010-12-23 | 2011-06-24 | $3760.00 | Window Closed / Lapsed |
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