Apparatus and method for generating an oscillating signal

Claim 2

An oscillator for driving at least one charge pump circuit, comprising: an oscillator for generating at an output terminal an output signal that oscillates between first and second logic states, the oscillator circuit providing the output signal in response to an active control signal; a shift register having at least two shift register stages coupled in series through which data is shifted in response to the output signal of the oscillator, each shift register stage having a control terminal coupled to the output of the oscillator and further having input and output terminals, the output terminal of a last shift register stage coupled to the input terminal of a first shift register stage, each shift register stage shifting data from the input terminal to the output terminal in response to the output signal of the oscillator having a logic state corresponding to a respective shift state; and a duty cycle corrector having input terminals, each input terminal coupled to a respective output terminal of a shift register stage, the duty cycle corrector further having a corresponding number of output terminals at which output signals for driving charge pumps are provided.

Claim 3

The oscillator of claim 1 , further comprising a reset circuit coupled to the shift register for resetting the logic state of at least one of the shift register stages in response to receiving an active reset signal.

Claim 4

The oscillator of claim 1 wherein the shift register stage comprises first, second, third, fourth, fifth, and sixth shift register stages coupled in series, the first, third, and fifth stages shifting data in response to the output signal of the oscillator having the first logic state, and the second fourth and sixth stages shifting data in response to the output signal of the oscillator having the second logic stage.

Claim 5

The oscillator of claim 1 wherein each of the shift register stages comprises: a latch circuit having an input and output for latching data applied to its input; and a transfer gate through which data is provided to the input of the latch circuit in response to the signal applied to the control terminal having a logic state corresponding to a shift state.

Claim 6

The oscillator of claim 1 wherein the duty cycle corrector reduces the frequency of the oscillator by one-third.

Claim 7

The oscillator of claim 1 wherein the duty cycle corrector comprises a plurality of duty cycle corrector stages, each stage having first and second inputs coupled to the output of a first and a second shift register stage, respectively, the logic state of an output signal of a duty cycle corrector stage based on the logic states of the outputs of the first and second shift register stages to which the stage is coupled.

Claim 8

The oscillator of claim 1 wherein the duty cycle corrector provides a plurality of periodic output signals having a common period, the respective periodic output signals transitioning to a HIGH logic level at times equally spaced throughout the common period.

Claim 9

The oscillator of claim 1 wherein the output signals of the duty cycle corrector are provided in an output sequence, the output sequence interrupted in response to the control signal becoming inactive and continuing from where the output sequence was interrupted in response to the control signal becoming active again.

Claim 10

An oscillator for providing a plurality of oscillating output signals, comprising: an oscillator having control and output terminals, the oscillator providing at the output terminal an output signal oscillating between first and second logic levels in response to an active control signal applied to the control terminal; and a shift register having a plurality of output terminals at which a respective oscillating output signal is provided, the shift register further having a shift terminal coupled to the output terminal of the oscillator and shifting data from one output terminal to another in response to the output signal of the oscillator oscillating between the first and second logic levels.

Claim 11

An oscillator for providing a plurality of oscillating output signals, comprising: an oscillator having control and output terminals, the oscillator providing at the output terminal an output signal oscillating between first and second logic levels in response to an active control signal applied to the control terminal; and a shift register having a plurality of output terminals at which a respective oscillating output signal is provided, the shift register further having a shift terminal coupled to the output terminal of the oscillator and shifting data from one output terminal to another in response to the output signal of the oscillator oscillating between the first and second logic levels.

Claim 12

The oscillator of claim 9 wherein the shift register comprises a plurality of shift register stages coupled in series, every other shift register stage latching data in response to the output signal of the oscillator having the first logic level, and the remaining shift register stages latching data in response to the output signal of the oscillator having the second logic level.

Claim 13

The oscillator of claim 9 wherein the shift register comprises a plurality of shift register stages, each shift register stage having a transfer gate and a pair of inverters coupled in series to one another, the transfer gate providing the pair of inverters data to be latched.

Claim 14

The oscillator of claim 9 , further comprising a duty cycle corrector coupled to the output terminals of the shift register and having output terminals to provide output signals having a frequency a fraction of the frequency of the output signal of the oscillator.

Claim 15

The oscillator of claim 12 wherein the duty cycle corrector comprises a plurality of duty cycle corrector stages, each stage having first and second inputs coupled to a first and a second of the output terminals of the shift register, respectively, the logic state of an output signal of a duty cycle corrector stage based on the logic states of the output signals of the first and second output terminals to which the duty cycle corrector stage is coupled.

Claim 16

The oscillator of claim 13 wherein a duty cycle corrector stage comprises a two-input NOR logic gate having a first input coupled to an output of an inverter and a second input coupled to an output of a pair of series coupled inverters.

Claim 19

The apparatus of claim 15 wherein the duty cycle corrector further generates the output signals having a common period and according to an output sequence where the output signals transition from the first to second logic states at even intervals throughout the common period.

Claim 20

The apparatus of claim 15 wherein each of the shift register stages comprises: a latch circuit having an input and output for latching data applied to its input; and a transfer gate through which data is provided to the input of the latch circuit in response to the signal applied to the control terminal having a logic state corresponding to a shift state.

Claim 21

The apparatus of claim 17 wherein the transfer gate of adjacent shift register stages couple a logic state to the input of the respective latch in response to opposite logic states of the oscillating signal.

Claim 22

The apparatus of claim 15 wherein every other shift register stage of the plurality shifts a latched logic state in response to the oscillating signal having the first logic state, and the remaining shift register stages of the plurality shifts a latched logic state in response to the oscillating signal having the second logic state.

Claim 23

The apparatus of claim 15 , further comprising a reset circuit coupled to at least one of the shift register stages to set the respective latch to a predetermined logic state.

Claim 24

The apparatus of claim 15 wherein the duty cycle corrector comprises a two input logic gate having a first input coupled to the output of a first of the shift register stages and a second input coupled to the output of a second of the shift register stages.

Claim 25

The apparatus of claim 21 wherein the duty cycle corrector generates output signals having a frequency one-third of the oscillating signal.

Claim 26

A memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; an oscillator circuit for generating a signal oscillating between a first and second logic state; and an apparatus coupled to the oscillator circuit for generating a plurality of output signals for driving a corresponding plurality of charge pumps from the oscillating signal, the apparatus comprising: a plurality of shift register stages coupled in series, each shift register stage having a control terminal for receiving the oscillating signal and further having input and output terminals, a last shift register stage having the output coupled to the input of a first shift register stage, the shift register stages shifting a latched logic state from the input terminal to the output terminal in response to the oscillating signal; and a duty cycle corrector having input terminals coupled to the output terminals of the shift register stages and output terminals at which the plurality of output signals are provided, the duty cycle corrector generating each of the output signals based on the latched logic state of two of the shift register stages.

Claim 27

A memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; an oscillator circuit for generating a signal oscillating between a first and second logic state; and an apparatus coupled to the oscillator circuit for generating a plurality of output signals for driving a corresponding plurality of charge pumps from the oscillating signal, the apparatus comprising: a plurality of shift register stages coupled in series, each shift register stage having a control terminal for receiving the oscillating signal and further having input and output terminals, a last shift register stage having the output coupled to the input of a first shift register stage, the shift register stages shifting a latched logic state from the input terminal to the output terminal in response to the oscillating signal; and a duty cycle corrector having input terminals coupled to the output terminals of the shift register stages and output terminals at which the plurality of output signals are provided, the duty cycle corrector generating each of the output signals based on the latched logic state of two of the shift register stages.

Claim 28

The memory device of claim 23 wherein the duty cycle corrector of the apparatus further generates the output signals having a common period and according to an output sequence where the output signals transition from the first to second logic states at even intervals throughout the common period.

Claim 29

The memory device of claim 23 wherein each of the shift register stages of the apparatus comprises: a latch circuit having an input and output for latching data applied to its input; and a transfer gate through which data is provided to the input of the latch circuit in response to the signal applied to the control terminal having a logic state corresponding to a shift state.

Claim 30

The memory device of claim 25 wherein the transfer gate of adjacent shift register stages couple a logic state to the input of the respective latch in response to opposite logic states of the oscillating signal.

Claim 31

The memory device of claim 23 wherein every other shift register stage of the plurality shifts a latched logic state in response to the oscillating signal having the first logic state, and the remaining shift register stages of the plurality shifts a latched logic state in response to the oscillating signal having the second logic state.

Claim 32

The memory device of claim 23 wherein the apparatus further comprises a reset circuit coupled to at least one of the shift register stages to set the respective latch to a predetermined logic state.

Claim 33

The memory device of claim 23 wherein the duty cycle corrector of the apparatus comprises a two input logic gate having a first input coupled to the output of a first of the shift register stages and a second input coupled to the output of a second of the shift register stages.

Claim 34

The memory device of claim 29 wherein the duty cycle corrector of the apparatus generates output signals having a frequency one-third of the oscillating signal.

Claim 35

A computer system, comprising: a data input device; a data output device; a processor coupled to the data input and output devices; and a memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; an oscillator circuit for generating a signal oscillating between a first and second logic state; and an apparatus coupled to the oscillator circuit for generating a plurality of output signals for driving a corresponding plurality of charge pumps from the oscillating signal, the apparatus comprising: a plurality of shift register stages coupled in series, each shift register stage having a control terminal for receiving the oscillating signal and further having input and output terminals, a last shift register stage having the output coupled to the input of a first shift register stage, the shift register stages shifting a latched logic state from the input terminal to the output terminal in response to the oscillating signal; and a duty cycle corrector having input terminals coupled to the output terminals of the shift register stages and output terminals at which the plurality of output signals are provided, the duty cycle corrector generating each of the output signals based on the latched logic state of two of the shift register stages.

Claim 36

A computer system, comprising: a data input device; a data output device; a processor coupled to the data input and output devices; and a memory device, comprising: an address bus; a control bus; a data bus; an address decoder coupled to the address bus; a read/write circuit coupled to the data bus; a memory-cell array coupled to the address decoder, control circuit, and read/write circuit; an oscillator circuit for generating a signal oscillating between a first and second logic state; and an apparatus coupled to the oscillator circuit for generating a plurality of output signals for driving a corresponding plurality of charge pumps from the oscillating signal, the apparatus comprising: a plurality of shift register stages coupled in series, each shift register stage having a control terminal for receiving the oscillating signal and further having input and output terminals, a last shift register stage having the output coupled to the input of a first shift register stage, the shift register stages shifting a latched logic state from the input terminal to the output terminal in response to the oscillating signal; and a duty cycle corrector having input terminals coupled to the output terminals of the shift register stages and output terminals at which the plurality of output signals are provided, the duty cycle corrector generating each of the output signals based on the latched logic state of two of the shift register stages.

Claim 37

The computer system of claim 31 wherein the duty cycle corrector of the apparatus further generates the output signals having a common period and according to an output sequence where the output signals transition from the first to second logic states at even intervals throughout the common period.

Claim 38

The computer system of claim 31 wherein each of the shift register stages of the apparatus comprises: a latch circuit having an input and output for latching data applied to its input; and a transfer gate through which data is provided to the input of the latch circuit in response to the signal applied to the control terminal having a logic state corresponding to a shift state.

Claim 39

The computer system of claim 33 wherein the transfer gate of adjacent shift register stages couple a logic state to the input of the respective latch in response to opposite logic states of the oscillating signal.

Claim 40

The computer system of claim 31 wherein every other shift register stage of the plurality shifts a latched logic state in response to the oscillating signal having the first logic state, and the remaining shift register stages of the plurality shifts a latched logic state in response to the oscillating signal having the second logic state.

Claim 41

The computer system of claim 31 wherein the apparatus further comprises a reset circuit coupled to at least one of the shift register stages to set the respective latch to a predetermined logic state.

Claim 42

The computer system of claim 31 wherein the duty cycle corrector of the apparatus comprises a two input logic gate having a first input coupled to the output of a first of the shift register stages and a second input coupled to the output of a second of the shift register stages.

Claim 43

The computer system of claim 37 wherein the duty cycle corrector of the apparatus generates output signals having a frequency one-third of the oscillating signal.

Claim 46

The method of claim 39 wherein generating each of the oscillating output signals comprises generating the oscillating output signals having a common period and in an output sequence where the output signals transition from the first to second logic states at even intervals throughout the common period.

Claim 47

The method of claim 39 wherein latching and shifting data comprises: latching data in response to the oscillating signal having the first logic state; and shifting data in response to the oscillating signal having the second logic state.

Claim 48

The method of claim 39 wherein latching and shifting data of adjacent shift register stages occurs in response to opposite logic states of the oscillating signal.

Claim 49

The method of claim 39 wherein generating the oscillating output signals comprises performing a logical operation on the latched logic states of two of the shift register stages.

Claim 50

The method of claim 43 wherein performing a logical operation results in producing oscillating output signals having a frequency one-third of the oscillating signal.

Claim 53

The method of claim 45 wherein generating the plurality of output signals comprises performing a logical operation on the latched logic states of two of the shift register stages.

Claim 54

The method of claim 45 wherein latching and shifting data comprises: latching data in response to the oscillating signal having the first logic state; and shifting data in response to the oscillating signal having the second logic state.

Claim 55

The method of claim 45 wherein latching and shifting data of adjacent shift register stages occurs in response to opposite logic states of the oscillating signal.