Numerically controlled oscillator

Claim 2

A numerically controlled oscillator comprising: means for providing an input indicative of a frequency; a plurality of adding units, each adding unit comprising a one bit adder having a first input, having a second input, and having a third input, said third input being coupled to said means for providing an input indicative of a frequency, having a sum output, and having a carry output and a register having a clock input, having a first input coupled to said sum output of said adder, having a second input coupled to said carry output of said adder, having a sum output coupled to said first input of said adder and having a carry output; said adding units being coupled in series with a first unit in said series having said second input of said adder tied to a source of a logic level signal and with each consecutive unit having a second input of an adder coupled to a carry output of a register in a previous unit in said series; and means for providing an output coupled to each of said sum outputs of each of said registers.

Claim 3

The numerically controlled oscillator as recited in claim 1 wherein each of said adders comprises a plurality of logic gates, and said means for storing comprises a plurality of latches, each latch being coupled to at least one of said logic gates, each latch having an output, means for logically combining said outputs of said latches to provide said sum output and said carry complement output of said register.

Claim 4

A fast parallel adder comprising: a first stage having means for adding input signals with means for accepting a frequency input, with means for accepting a sum input, and with means for accepting a carry input, and having means for storing the result of an addition with a clock input, with means for providing a sum output and with means for providing a carry output; and a second stage having means for adding inputs signals with means for accepting a frequency input, with means for accepting a sum input coupled to said means for providing a sum output of said first stage, with means for accepting a carry input, and having means for storing the result of an addition with means for providing a sum output coupled to said means for accepting a sum input of said first stage and with means for providing a carry output, said clock input of said first stage being suitable for application of a first clock signal and said clock input of said second stage being suitable for application of a second clock signal out of phase with said first clock signal so that the result of an addition in said means for adding of said first stage is stored upon application of said first clock signal tp said first stage and so that the result of an addition in said second stage is stored upon application of said second clock signal to said second stage.

Claim 5

A fast parallel adder comprising: a first stage having means for adding input signals with means for accepting a frequency input, with means for accepting a sum input, and with means for accepting a carry input, and having means for storing the result of an addition with a clock input, with means for providing a sum output and with means for providing a carry output; and a second stage having means for adding inputs signals with means for accepting a frequency input, with means for accepting a sum input coupled to said means for providing a sum output of said first stage, with means for accepting a carry input, and having means for storing the result of an addition with means for providing a sum output coupled to said means for accepting a sum input of said first stage and with means for providing a carry output, said clock input of said first stage being suitable for application of a first clock signal and said clock input of said second stage being suitable for application of a second clock signal out of phase with said first clock signal so that the result of an addition in said means for adding of said first stage is stored upon application of said first clock signal tp said first stage and so that the result of an addition in said second stage is stored upon application of said second clock signal to said second stage.

Claim 6

The fast parallel adder, as recited in claim 3 wherein in said first stage said means for accepting a frequency input comprises a frequency input and a frequency complement input, said means for accepting a sum input comprises a sum input and a sum complement input, said means for accepting a carry input comprises a carry input and a carry complement input, said means for providing a sum output comprises a sum output and a sum complement output, and said means for providing a carry output comprises a carry output and a carry complement output; and wherein in said second stage said means for accepting a frequency input comprises a frequency input and a frequency complement input, said means for accepting a sum input comprises a sum input and a sum complement input, said means for accepting a carry input comprises a carry input and a carry complement input, said means for providing a sum output comprises a sum output and a sum complement output, and said means for providing a carry output comprises a carry output and a carry complement output.

Claim 7

The fast parallel adder as recited in claim 4 wherein said means for adding of said first stage comprises a plurality of logic gates wherein said means for storing comprises a plurality of latches, each latch being coupled to at least one of said logic gates, each latch having an output means for logically combining said outputs of said latches to provide said sum output, said sum complement output, said carry output and said carry complement output of said first stage; and wherein said means for adding of said second stage comprises a plurality of logical gates; and wherein said means for storing comprises a plurality of latches, each latch being coupled to at least one of said logic gates, each latch having an output, means for logically combining said outputs of said latches to provide said sum output said sum complement output, said carry output and said carry complement output of said stage.

Claim 8

A numerically controlled oscillator capable of operating at radio frequencies comprising: means for providing an input indicative of a frequency; a plurality of registers; a plurality of adding units, each adding unit having a first stage and a second stage, each of said first stages having means for adding input signals with means for accepting a frequency input, with means for accepting a sum input, and with means for accepting a carry input, and having means for storing the result of an addition with a clock input, with means for providing a sum output and with means for providing a carry output; each of said second stages having means for adding input signals with means for accepting a frequency input, with means for accepting a sum input coupled to said means for providing a sum output of said first stage, and with means for accepting a carry input, and having means for storing the result of an addition with a clock input, with means for providing a sum output coupled to said means for accepting a sum input of said first stage, and with means for providing a carry output; said clock input of said first stage being suitable for application of a first clock signal and said clock input of said second stage being suitable for application of a second clock signal out of phase with said first clock signal so that the result of an addition in said means for adding of said first stage is stored upon application of a first clock signal to said first stage and so that the result of an addition in said means for adding of said second stage is stored upon application of said second clock signal to said second stage; said adding units each being coupled to a register and the combination being coupled in series, with a first unit in said series having said carry input of said adder coupled to a source of a logic level signal and with each consecutive unit having a second input of an adder coupled to a carry output of a register in a previous unit in said series; and means for providing an output coupled to each of said sum outputs of each of said registers.

Claim 9

A numerically controlled oscillator capable of operating at radio frequencies comprising: means for providing an input indicative of a frequency; a plurality of registers; a plurality of adding units, each adding unit having a first stage and a second stage, each of said first stages having means for adding input signals with means for accepting a frequency input, with means for accepting a sum input, and with means for accepting a carry input, and having means for storing the result of an addition with a clock input, with means for providing a sum output and with means for providing a carry output; each of said second stages having means for adding input signals with means for accepting a frequency input, with means for accepting a sum input coupled to said means for providing a sum output of said first stage, and with means for accepting a carry input, and having means for storing the result of an addition with a clock input, with means for providing a sum output coupled to said means for accepting a sum input of said first stage, and with means for providing a carry output; said clock input of said first stage being suitable for application of a first clock signal and said clock input of said second stage being suitable for application of a second clock signal out of phase with said first clock signal so that the result of an addition in said means for adding of said first stage is stored upon application of a first clock signal to said first stage and so that the result of an addition in said means for adding of said second stage is stored upon application of said second clock signal to said second stage; said adding units each being coupled to a register and the combination being coupled in series, with a first unit in said series having said carry input of said adder coupled to a source of a logic level signal and with each consecutive unit having a second input of an adder coupled to a carry output of a register in a previous unit in said series; and means for providing an output coupled to each of said sum outputs of each of said registers.

Claim 10

The numerically controlled oscillator as recited in claim 6 wherein in said first stage said means for accepting a frequency input comprises a frequency input and a frequency complement input, wherein said means for accepting a sum input comprises a sum input and a sum complement input, wherein said means for accepting a carry input comprises a carry input and a carry complement input, wherein said means for providing a sum output comprises a sum output and a sum complement output, and wherein said means for providing a carry output comprises a carry output and a carry complement output; and wherein in said means for adding of said second stage said means for accepting a frequency input comprises a frequency input and a frequency complement input, wherein said means for accepting a sum input comprises a sum input and a sum complement input, wherein said means for accepting a carry input comprises a carry input and a carry complement input, wherein said means for providing a sum output comprises a sum output and a sum complement output, and wherein said means for providing a carry output comprise a carry output and a carry complement output.

Claim 11

The numerically controlled oscillator as recited in claim 7 wherein said means for adding of said first stage comprises a plurality of logic gates, wherein said means for storing comprises a plurality of latches, each latch coupled to at least one of said logic gates, each latch having an output, means for logically combining said outputs of said latches to provide said sum output, said sum complement out, said carry output and said carry complement output of said first stage; and wherein said means for adding of said second stage comprises a plurality of logic gates, and wherein said means for storing comprises a plurality of latches, each latch being coupled to at least one of said logic gates, each latch having an output, means for logically combining said outputs of said latches to provide said sum output, said sum complement output, said carry output and said carry complement output of said second stage.