US4144579A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Arithmetic synthesizer frequency generation with reduced phase jitter
Assignee: RCA Corp
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Filing: 1977-07-25
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Granted: 1979-03-13
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Expires: 1997-07-25
Abstract
Abstract Arithmetic synthesizer having an output circuit that provides a linear phase output signal. A ramp generator controlled by the stepped output signal from the arithmetic synthesizer interpolates the value of the signal slope between steps to supply a phase output having low noise, i.e., reduced time jitter.
Inventors
- 👤 Edward J. Nossen
- 👤 Eugene R. Starner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:56
CPC Classifications
G; G06; G06J; G06J1/00; H; H03; H03K; H03K4/00; H03K4/06; H03K4/08; H03K4/48; H03K4/50; H03K4/501; H03K4/502; H03K4/56; H03K6/00; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/091; H03L7/16; H03L7/18; H03L7/1806
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
135 words
In an arithmetic synthesizer including means for supplying digital signals representing a frequency number, means for supplying clock signals, accumulator means for periodically accumulating said digital signals representing a frequency number to produce digital sum signals having a given modulus, and digital-to-analog conversion means receptive of said digital sum signals for producing analog signals representative of said digital sum signals, the improvement comprising: output means responsive to said analog signals for producing output signals representing the instantaneous value of the average slope of said digital signals; said output means including means for mixing said output signals and said digital signals to produce difference signals; and said output means further including sweep generator means responsive to said difference signals for producing said output signals having a linear slope determined by the value of said difference signals.
Claim 2
Dependent Claim
135 words
In an arithmetic synthesizer including means for supplying digital signals representing a frequency number, means for supplying clock signals, accumulator means for periodically accumulating said digital signals representing a frequency number to produce digital sum signals having a given modulus, and digital-to-analog conversion means receptive of said digital sum signals for producing analog signals representative of said digital sum signals, the improvement comprising: output means responsive to said analog signals for producing output signals representing the instantaneous value of the average slope of said digital signals; said output means including means for mixing said output signals and said digital signals to produce difference signals; and said output means further including sweep generator means responsive to said difference signals for producing said output signals having a linear slope determined by the value of said difference signals.
Claim 3
Dependent Claim
46 words
The invention as claimed in claim 1 wherein said sweep generator means includes: current generating means responsive to said difference signals for supplying a current determined by the value of said difference signals; and capacitor means coupled to receive said current for producing said output signals.
Claim 4
Dependent Claim
15 words
The invention as claimed in claim 2 wherein said current generating means includes integrator means.
Claim 5
Dependent Claim
28 words
The invention as claimed in claim 2 further including holding means responsive to said clock signals for storing the value of said difference signals between successive clock signals.
Claim 6
Dependent Claim
67 words
The invention as claimed in claim 4 including: means for producing a reference signal related to a maximum value of said output signals; means for comparing said output signals to said reference signal for producing a discharge signal when said output signals are not less than said reference signal; and means coupled across said capacitor means for discharging said output signal in response to said discharge signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-03-12 | 1982-09-11 | 1983-03-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-03-12 | 1986-09-11 | 1987-03-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-03-12 | 1990-09-11 | 1991-03-13 | $7700.00 | Window Closed / Lapsed |