US6560725B1
Expired / Lapsed
US
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Method for apparatus for tracking errors in a memory system
Assignee: Madrone Solutions Inc
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Filing: 1999-06-18
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Granted: 2003-05-06
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Expires: 2019-06-18
Abstract
Abstract A method for tracking errors in a memory system by detecting an error in a bit of a word accessed in the memory and maintaining an error history comprising a record of each of the detected errors. The error history information may be used to configure the memory, such as to add redundancy; or may be used to adjust operating parameters of the memory, such as the periodicity of refresh and/or scrub operations; or may be used to trigger a sensing operation of other parameters in an application system. In one embodiment, a counter increments each time an error is detected and decrements when no error is detected, thereby tracking error patterns.
Inventors
- 👤 Michael L. Longwell
- 👤 William Daune Atwell
- 👤 Jeffrey Van Myers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:48
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0766; G06F11/0772; G06F11/0706; G06F11/073; G11; G11C; G11C29/00; G11C29/02; G11C29/028; G11C29/04; G11C29/50; G11C29/50016; G11C29/56; G11C29/56012; G06F11/0751; G06F11/0754; G06F11/076; G06F2201/00; G06F2201/88; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
110 words
In a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, an error detection and tracking circuit comprising: an error detection circuit connected to the memory to detect an error in a bit of a word accessed in the memory; and a tracking unit connected to the error detection circuit, wherein the tracking unit: maintains an error history comprising: a record of each word accessed in said memory in which an error is detected; and a record of each word accessed in said memory in which no error is detected; and periodically discards the oldest of said records in said error history.
Claim 2
Dependent Claim
110 words
In a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, an error detection and tracking circuit comprising: an error detection circuit connected to the memory to detect an error in a bit of a word accessed in the memory; and a tracking unit connected to the error detection circuit, wherein the tracking unit: maintains an error history comprising: a record of each word accessed in said memory in which an error is detected; and a record of each word accessed in said memory in which no error is detected; and periodically discards the oldest of said records in said error history.
Claim 3
Dependent Claim
15 words
The memory system of claim 1 wherein the error detection circuit corrects detected single-bit errors.
Claim 4
Dependent Claim
14 words
The memory system of claim 2 wherein the error detection circuit detects multi-bit errors.
Claim 5
Dependent Claim
36 words
The memory system of claim 1 wherein the tracking unit periodically discards the oldest of said records so that the error history comprises the records of only those detected errors recorded during a current tracking window.
Claim 6
Dependent Claim
29 words
The memory system of claim 4 wherein the tracking unit asserts an error signal when the number of errors recorded in the current tracking window exceeds a predetermined threshold.
Claim 7
Dependent Claim
25 words
The memory system of claim 1 wherein said record includes the location in the memory of the word in which said error bit was detected.
Claim 8
Dependent Claim
15 words
The memory system of claim 6 wherein said record indicates the nature of said error.
Claim 9
Dependent Claim
18 words
The memory system of claim 1 wherein the tracking unit selectively forwards said records in said error history.
Claim 10
Dependent Claim
40 words
The memory system of claim 1 further comprising: a refresh controller connected to the memory to periodically refresh each word stored in the memory; and wherein the tracking unit controls the refresh periodicity as a function of the error history.
Claim 11
Dependent Claim
40 words
The memory system of claim 1 further comprising: a scrub controller connected to the memory to periodically scrub each word stored in the memory; and wherein the tracking unit controls the scrub periodicity as a function of the error history.
Claim 12
Dependent Claim
130 words
An error detection and tracking circuit for use in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, said memory further comprising a selectively enabled redundant bit, the circuit comprising: an error detection circuit connected to the memory to detect an error in a bit of a word accessed in the memory; a tracking unit connected to the error detection circuit, wherein the tracking unit maintains an error history comprising a record of each said detected errors; and a control circuit connected to the tracking unit and to the memory, to control the operation of said memory as a function of said error history; and wherein the control circuit selectively enables said redundant bit as a function of the error history.
Claim 13
Dependent Claim
130 words
An error detection and tracking circuit for use in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, said memory further comprising a selectively enabled redundant bit, the circuit comprising: an error detection circuit connected to the memory to detect an error in a bit of a word accessed in the memory; a tracking unit connected to the error detection circuit, wherein the tracking unit maintains an error history comprising a record of each said detected errors; and a control circuit connected to the tracking unit and to the memory, to control the operation of said memory as a function of said error history; and wherein the control circuit selectively enables said redundant bit as a function of the error history.
Claim 14
Dependent Claim
128 words
An error detection and tracking circuit for use in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, said memory further comprising a selectively enabled sensor, the circuit comprising: an error detection circuit connected to the memory to detect an error in a bit of a word accessed in the memory; a tracking unit connected to the error detection circuit, wherein the tracking unit maintains an error history comprising a record of each said detected errors; and a control circuit connected to the tracking unit and to the memory, to control the operation of said memory as a function of said error history; and wherein the control circuit selectively enables said sensor as a function of the error history.
Claim 15
Dependent Claim
128 words
An error detection and tracking circuit for use in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, said memory further comprising a selectively enabled sensor, the circuit comprising: an error detection circuit connected to the memory to detect an error in a bit of a word accessed in the memory; a tracking unit connected to the error detection circuit, wherein the tracking unit maintains an error history comprising a record of each said detected errors; and a control circuit connected to the tracking unit and to the memory, to control the operation of said memory as a function of said error history; and wherein the control circuit selectively enables said sensor as a function of the error history.
Claim 16
Dependent Claim
155 words
An error detection and tracking circuit for use in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, the circuit comprising: an error detection circuit connected to the memory to detect an error in a bit of a word accessed in the memory; a tracking unit connected to the error detection circuit, wherein the tracking unit maintains an error history comprising a record of each said detected errors; a memory controller connected to the memory, the error detection circuit and the tracking unit, to control an access to the memory during an access cycle, at least one parameter of which is controllable; and a control circuit connected to the tracking unit and to the memory controller, to control the operation of said memory controller as a function of said error history; and wherein the control circuit controls said parameter as a function of the error history.
Claim 17
Dependent Claim
155 words
An error detection and tracking circuit for use in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, the circuit comprising: an error detection circuit connected to the memory to detect an error in a bit of a word accessed in the memory; a tracking unit connected to the error detection circuit, wherein the tracking unit maintains an error history comprising a record of each said detected errors; a memory controller connected to the memory, the error detection circuit and the tracking unit, to control an access to the memory during an access cycle, at least one parameter of which is controllable; and a control circuit connected to the tracking unit and to the memory controller, to control the operation of said memory controller as a function of said error history; and wherein the control circuit controls said parameter as a function of the error history.
Claim 18
Dependent Claim
124 words
An error detection and tracking circuit for use in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, the circuit comprising: an error detection circuit connected to the memory to detect an error in a bit of a word accessed in the memory; a tracking unit connected to the error detection circuit, wherein the tracking unit maintains an error history comprising a record of each said detected errors; and a control circuit connected to the tracking unit and to the memory, to control the operation of said memory as a function of said error history; and wherein the control circuit selectively disables a selected portion of the memory as a function of the error history.
Claim 19
Dependent Claim
124 words
An error detection and tracking circuit for use in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, the circuit comprising: an error detection circuit connected to the memory to detect an error in a bit of a word accessed in the memory; a tracking unit connected to the error detection circuit, wherein the tracking unit maintains an error history comprising a record of each said detected errors; and a control circuit connected to the tracking unit and to the memory, to control the operation of said memory as a function of said error history; and wherein the control circuit selectively disables a selected portion of the memory as a function of the error history.
Claim 20
Independent Claim
72 words
A method for tracking errors in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, the method comprising the steps of: detecting an error in a bit of a word accessed in the memory; maintaining an error history comprising a record of each of said detected errors; and selectively enabling a redundant bit in the memory as a function of the error history.
Claim 21
Independent Claim
72 words
A method for tracking errors in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, the method comprising the steps of: detecting an error in a bit of a word accessed in the memory; maintaining an error history comprising a record of each of said detected errors; and selectively enabling a redundant bit in the memory as a function of the error history.
Claim 22
Independent Claim
75 words
A method for tracking errors in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, the method comprising the steps of: detecting an error in a bit of a word accessed in the memory; maintaining an error history comprising a record of each of said detected errors; and selectively controlling a parameter of an access cycle to the memory as a function of the error history.
Claim 23
Independent Claim
75 words
A method for tracking errors in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, the method comprising the steps of: detecting an error in a bit of a word accessed in the memory; maintaining an error history comprising a record of each of said detected errors; and selectively controlling a parameter of an access cycle to the memory as a function of the error history.
Claim 24
Independent Claim
72 words
A method for tracking errors in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, the method comprising the steps of: detecting an error in a bit of a word accessed in the memory; maintaining an error history comprising a record of each of said detected errors; and selectively disabling a selected portion of the memory as a function of the error history.
Claim 25
Independent Claim
72 words
A method for tracking errors in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, the method comprising the steps of: detecting an error in a bit of a word accessed in the memory; maintaining an error history comprising a record of each of said detected errors; and selectively disabling a selected portion of the memory as a function of the error history.
Claim 26
Independent Claim
68 words
A method for tracking errors in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, the method comprising the steps of: detecting an error in a bit of a word accessed in the memory; maintaining an error history comprising a record of each of said detected errors; and selectively enabling a sensor as a function of the error history.
Claim 27
Independent Claim
68 words
A method for tracking errors in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, the method comprising the steps of: detecting an error in a bit of a word accessed in the memory; maintaining an error history comprising a record of each of said detected errors; and selectively enabling a sensor as a function of the error history.
Claim 28
Independent Claim
96 words
A method for tracking errors in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, the method comprising the steps of: detecting an error in a bit of a word accessed in the memory; maintaining an error history comprising a record of each of said detected errors; controlling the operation of said memory as a function of said error history; and periodically discarding the oldest of said records so that the error history comprises the records of only those detected errors recorded during a current tracking window.
Claim 29
Independent Claim
96 words
A method for tracking errors in a memory system having a memory for storing a plurality of words, each comprising a plurality of bits, the method comprising the steps of: detecting an error in a bit of a word accessed in the memory; maintaining an error history comprising a record of each of said detected errors; controlling the operation of said memory as a function of said error history; and periodically discarding the oldest of said records so that the error history comprises the records of only those detected errors recorded during a current tracking window.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2006-05-05 | 2006-11-04 | 2007-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-05-05 | 2010-11-04 | 2011-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-05-05 | 2014-11-04 | 2015-05-06 | $7700.00 | Window Closed / Lapsed |