US6559548B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wiring structure of semiconductor device
Assignee: Toshiba Corp
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Filing: 2000-03-16
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Granted: 2003-05-06
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Expires: 2020-03-16
Abstract
Abstract A wiring layer is covered with a first organic SOG layer, a reinforcement insulating layer consisting of a silicon oxide film or a silicon nitride film formed by means of a plasma CVD method, and a second organic SOG layer, in this order. A via hole is formed in the first organic SOG layer and the reinforcement insulating layer, and a trench is formed in the second organic SOG layer to correspond to the via hole. A conductive via plug and an electrode pad are embedded in the via hole and the trench, respectively. The second SOG layer is covered with a passivation layer in which a through hole is formed to expose the electrode pad. A wire is connected to the exposed electrode pad in the through hole.
Inventors
- 👤 Noriaki Matsunaga
- 👤 Takamasa Usui
- 👤 Sachiyo Ito
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:00
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/071; H10W20/00; H10W20/01; H10W20/071; H10W20/074; H10W20/076; H10W20/081; H10W20/084; H10W20/40; H10W20/45; H10W20/47; H10W20/48; H10W72/01; H10W72/019; H10W72/20; H10W20/41; H10W20/425; H10W70/00; H10W70/60; H10W72/075; H10W72/07531; H10W72/07532; H10W72/251; H10W72/29; H10W72/50; H10W72/531; H10W72/5363; H10W72/551; H10W72/552; H10W72/5524; H10W72/5525; H10W72/59; H10W72/90; H10W72/921; H10W72/922; H10W72/923; H10W72/9232; H10W72/951; H10W72/952; H10W72/981; H10W72/983
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
229 words
A wiring structure of a semiconductor device comprising: a first insulating layer disposed on or above a substrate and having a relative dielectric constant of 3.0 or less, and a Young's modulus of less than 50 GPa, the first insulating layer including a first recess formed in a surface of the first insulating layer and a first via hole formed therein; a wiring layer and a first via plug disposed in the first recess and the first via hole, respectively; a second insulating layer disposed on or above the first insulating layer and having a Young's modulus of 50 GPa or more, the second insulating layer including a second recess formed in a surface of the second insulating layer and a second via hole formed therein, the second recess and the second via hole being connected to each other at a second connecting portion disposed in the second insulating layer, the second recess having a width larger than that of the second via hole at the second connecting portion in a cross section; and an electrode pad and a second via plug disposed in the second recess and the second via hole, respectively, the electrode pad and the wiring layer being electrically connected to each other by the second via plug, the electrode pad being arranged to be electrically connected to a connecting member by bonding with applied pressure.
Claim 2
Dependent Claim
229 words
A wiring structure of a semiconductor device comprising: a first insulating layer disposed on or above a substrate and having a relative dielectric constant of 3.0 or less, and a Young's modulus of less than 50 GPa, the first insulating layer including a first recess formed in a surface of the first insulating layer and a first via hole formed therein; a wiring layer and a first via plug disposed in the first recess and the first via hole, respectively; a second insulating layer disposed on or above the first insulating layer and having a Young's modulus of 50 GPa or more, the second insulating layer including a second recess formed in a surface of the second insulating layer and a second via hole formed therein, the second recess and the second via hole being connected to each other at a second connecting portion disposed in the second insulating layer, the second recess having a width larger than that of the second via hole at the second connecting portion in a cross section; and an electrode pad and a second via plug disposed in the second recess and the second via hole, respectively, the electrode pad and the wiring layer being electrically connected to each other by the second via plug, the electrode pad being arranged to be electrically connected to a connecting member by bonding with applied pressure.
Claim 3
Dependent Claim
20 words
The structure according to claim 1 , wherein the second insulating layer has a thickness of 100 nm or more.
Claim 4
Dependent Claim
21 words
The structure according to claim 1 , wherein the first insulating layer has a Young's modulus of 10 GPa or less.
Claim 5
Dependent Claim
22 words
The structure according to claim 1 , wherein the first insulating layer has a density of less than 2.0 g/cm 3 .
Claim 6
Dependent Claim
22 words
The structure according to claim 4 , wherein the first insulating layer consists essentially of a silicon oxide containing an organic material.
Claim 7
Dependent Claim
30 words
The structure according to claim 5 , wherein the second insulating layer consists essentially of a material selected from a group consisting of a silicon oxide or a silicon nitride.
Claim 8
Dependent Claim
55 words
The structure according to claim 1 , wherein the first recess and the first via hole are connected to each other at a first connecting portion disposed in the first insulating layer, the first recess having a width larger than that of the first via hole at the first connecting portion in a cross section.
Claim 9
Dependent Claim
57 words
The structure according to claim 1 , wherein the electrode pad and the first and second insulating layer are positionally and structurally combined for the second insulating layer to protect the first insulating layer from the pressure applied to the electrode pad and prevent a crack from being generated in the first insulating layer by the pressure.
Claim 10
Dependent Claim
223 words
A wiring structure of a semiconductor device comprising: a plurality of wiring layers disposed at different levels on or above a substrate; a plurality of first insulating layers disposed at levels substantially the same as those of the wiring layer of the different levels to surround the wiring layers, respectively, the first insulating layers each having a relative dielectric constant of 3.0 or less, and a Young's modulus of less than 50 GPa; a second insulating layer disposed on or above an uppermost first insulating layer located at an uppermost position among the first insulating layers, the second insulating layer having a Young's modulus of 50 GPa or more, the second insulating layer including a recess formed in a surface of the second insulating layer and a via hole formed therein, the recess and the via hole being connected to each other at a connecting portion disposed in the second insulating layer, the recess having a width larger than that of the via hole at the connecting portion in a cross section; and an electrode pad and a via plug disposed in the recess and the via hole, respectively, the electrode pad being electrically connected to one of the wiring layers by the via plug, the electrode pad being arranged to be electrically connected to a connecting member by bonding with applied pressure.
Claim 11
Dependent Claim
223 words
A wiring structure of a semiconductor device comprising: a plurality of wiring layers disposed at different levels on or above a substrate; a plurality of first insulating layers disposed at levels substantially the same as those of the wiring layer of the different levels to surround the wiring layers, respectively, the first insulating layers each having a relative dielectric constant of 3.0 or less, and a Young's modulus of less than 50 GPa; a second insulating layer disposed on or above an uppermost first insulating layer located at an uppermost position among the first insulating layers, the second insulating layer having a Young's modulus of 50 GPa or more, the second insulating layer including a recess formed in a surface of the second insulating layer and a via hole formed therein, the recess and the via hole being connected to each other at a connecting portion disposed in the second insulating layer, the recess having a width larger than that of the via hole at the connecting portion in a cross section; and an electrode pad and a via plug disposed in the recess and the via hole, respectively, the electrode pad being electrically connected to one of the wiring layers by the via plug, the electrode pad being arranged to be electrically connected to a connecting member by bonding with applied pressure.
Claim 12
Dependent Claim
20 words
The structure according to claim 9 , wherein the second insulating layer has a thickness of 100 nm or more.
Claim 13
Dependent Claim
21 words
The structure according to claim 9 , wherein the first insulating layer has a Young's modulus of 10 GPa or less.
Claim 14
Dependent Claim
22 words
The structure according to claim 9 , wherein the first insulating layer has a density of less than 2.0 g/cm 3 .
Claim 15
Dependent Claim
22 words
The structure according to claim 12 , wherein the first insulating layer consists essentially of a silicon oxide containing an organic material.
Claim 16
Dependent Claim
30 words
The structure according to claim 13 , wherein the second insulating layer consists essentially of a material selected from the group consisting of a silicon oxide and a silicon nitride.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-05-05 | 2006-11-04 | 2007-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-05-05 | 2010-11-04 | 2011-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-05-05 | 2014-11-04 | 2015-05-06 | $7700.00 | Window Closed / Lapsed |