Solving the poison via problem by adding N2 plasma treatment after via etching

Claim 1

The method of forming the intermetal dielectric layer of an integrated circuit while preventing outgassing from said intermetal dielectric layer comprising: forming semiconductor device structures in and on a semiconductor substrate; covering said semiconductor device structures with an insulating layer; depositing a first metal layer over said insulating layer and patterning said first metal layer; forming said intermetal dielectric layer comprising: covering said patterned first metal layer with a first layer of silicon oxide; covering said first silicon oxide layer with a layer of organic spin-on-glass material and curing said organic spin-on-glass layer to form an organic spin-on-glass silicon oxide layer; and covering said organic spin-on-glass silicon oxide layer with a second layer of silicon oxide to complete said intermetal dielectric layer; forming via openings through said intermetal dielectric layer to underlying said patterned first metal layer which thereby exposes portions of said organic -- spin-on-glass silicon oxide within said via openings; vacuum baking said semiconductor substrate to remove moisture from said exposed portions of said organic spin-on-glass silicon oxide layer within said via opening; thereafter exposing said organic spin-on-glass layer to nitrogen atoms in a vacuum of between about 4 to 8 Torr at a temperature of between about 350° to 450° C. for between about 10 to 50 seconds wherein said exposed portions of said organic spin-on-glass layer are converted to an inorganic material and wherein said inorganic material spin-on-glass layer prevents said outgassing from said intermetal dielectric layer; depositing a second metal layer overlying said intermetal dielectric layer and within said via openings; and completing fabrication of said integrated circuit.

Claim 2

The method of forming the intermetal dielectric layer of an integrated circuit while preventing outgassing from said intermetal dielectric layer comprising: forming semiconductor device structures in and on a semiconductor substrate; covering said semiconductor device structures with an insulating layer; depositing a first metal layer over said insulating layer and patterning said first metal layer; forming said intermetal dielectric layer comprising: covering said patterned first metal layer with a first layer of silicon oxide; covering said first silicon oxide layer with a layer of organic spin-on-glass material and curing said organic spin-on-glass layer to form an organic spin-on-glass silicon oxide layer; and covering said organic spin-on-glass silicon oxide layer with a second layer of silicon oxide to complete said intermetal dielectric layer; forming via openings through said intermetal dielectric layer to underlying said patterned first metal layer which thereby exposes portions of said organic -- spin-on-glass silicon oxide within said via openings; vacuum baking said semiconductor substrate to remove moisture from said exposed portions of said organic spin-on-glass silicon oxide layer within said via opening; thereafter exposing said organic spin-on-glass layer to nitrogen atoms in a vacuum of between about 4 to 8 Torr at a temperature of between about 350° to 450° C. for between about 10 to 50 seconds wherein said exposed portions of said organic spin-on-glass layer are converted to an inorganic material and wherein said inorganic material spin-on-glass layer prevents said outgassing from said intermetal dielectric layer; depositing a second metal layer overlying said intermetal dielectric layer and within said via openings; and completing fabrication of said integrated circuit.

Claim 8

The method of forming the intermetal dielectric layer of an integrated circuit while preventing outgassing from said intermetal dielectric layer comprising: forming semiconductor device structures in and on a semiconductor substrate; covering said semiconductor device structures with an insulating layer; depositing a first metal layer over said insulating layer and patterning said first metal layer; forming said intermetal dielectric layer comprising: covering said patterned first metal layer with a first layer of silicon oxide; covering said first silicon oxide layer with a layer of organic spin-on-glass material and curing said organic spin-on-glass layer to form an organic spin-on-glass silicon oxide layer; and covering said organic spin-on-glass silicon oxide layer with a second layer of silicon oxide to complete said intermetal dielectric layer; covering said intermetal dielectric layer with a layer of photoresist and patterning said photoresist layer to form a photoresist mask; etching via openings through said intermetal dielectric layer to underlying said patterned first metal layer using said photoresist mask wherein portions of said organic spin-on-glass silicon oxide within said via openings are exposed; removing said photoresist mask using oxygen plasma ashing wherein said oxygen plasma ashing generates moisture within said exposed portions of said organic spin-on-glass layer within said via openings; vacuum baking said semiconductor substrate to remove said moisture from said exposed portions of said organic spin-on-glass silicon oxide layer within said via openings; thereafter exposing said organic spin-on-glass layer to nitrogen atoms at a vacuum of between about 4 to 8 Torr at a temperature of between about 350° to 450° C. for between about 10 to 50 seconds wherein said exposed portions of said organic spin-on-glass layer are converted to an inorganic material and wherein said inorganic material spin-on-glass layer prevents said outgassing from said intermetal dielectric layer; depositing a second metal layer overlying said intermetal dielectric layer and within said via openings; and completing fabrication of said integrated circuit.

Claim 9

The method of forming the intermetal dielectric layer of an integrated circuit while preventing outgassing from said intermetal dielectric layer comprising: forming semiconductor device structures in and on a semiconductor substrate; covering said semiconductor device structures with an insulating layer; depositing a first metal layer over said insulating layer and patterning said first metal layer; forming said intermetal dielectric layer comprising: covering said patterned first metal layer with a first layer of silicon oxide; covering said first silicon oxide layer with a layer of organic spin-on-glass material and curing said organic spin-on-glass layer to form an organic spin-on-glass silicon oxide layer; and covering said organic spin-on-glass silicon oxide layer with a second layer of silicon oxide to complete said intermetal dielectric layer; covering said intermetal dielectric layer with a layer of photoresist and patterning said photoresist layer to form a photoresist mask; etching via openings through said intermetal dielectric layer to underlying said patterned first metal layer using said photoresist mask wherein portions of said organic spin-on-glass silicon oxide within said via openings are exposed; removing said photoresist mask using oxygen plasma ashing wherein said oxygen plasma ashing generates moisture within said exposed portions of said organic spin-on-glass layer within said via openings; vacuum baking said semiconductor substrate to remove said moisture from said exposed portions of said organic spin-on-glass silicon oxide layer within said via openings; thereafter exposing said organic spin-on-glass layer to nitrogen atoms at a vacuum of between about 4 to 8 Torr at a temperature of between about 350° to 450° C. for between about 10 to 50 seconds wherein said exposed portions of said organic spin-on-glass layer are converted to an inorganic material and wherein said inorganic material spin-on-glass layer prevents said outgassing from said intermetal dielectric layer; depositing a second metal layer overlying said intermetal dielectric layer and within said via openings; and completing fabrication of said integrated circuit.

Claim 15

The method of treating the intermetal dielectric layer of an integrated circuit to prevent outgassing from said intermetal dielectric layer comprising: providing an intermetal dielectric layer overlying a patterned first metal layer overlying an insulating layer covering semiconductor device structures in and on a semiconductor substrate wherein said intermetal dielectric layer comprises a first layer of silicon oxide, a layer of organic spin-on-glass material wherein said organic spin-on-glass layer is cured, and a second layer of silicon oxide and wherein via openings have been etched through said intermetal dielectric layer to underlying said patterned first metal layer wherein portions of said organic -- spin-on-glass layer within said via openings are exposed; vacuum baking said semiconductor substrate to remove moisture from said exposed portions of said organic -- spin-on-glass layer within said via openings; and thereafter exposing said organic spin-on-glass layer to nitrogen atoms at a vacuum of between about 4 to 8 Torr at a temperature of between about 350° to 450° C. for between about 10 to 50 seconds wherein said exposed portions of said organic spin-on-glass layer are converted to an inorganic material and wherein said inorganic material spin-on-glass layer prevents said outgassing from said intermetal dielectric layer to complete treatment of said intermetal dielectric layer in the fabrication of said integrated circuit.

Claim 16

The method of treating the intermetal dielectric layer of an integrated circuit to prevent outgassing from said intermetal dielectric layer comprising: providing an intermetal dielectric layer overlying a patterned first metal layer overlying an insulating layer covering semiconductor device structures in and on a semiconductor substrate wherein said intermetal dielectric layer comprises a first layer of silicon oxide, a layer of organic spin-on-glass material wherein said organic spin-on-glass layer is cured, and a second layer of silicon oxide and wherein via openings have been etched through said intermetal dielectric layer to underlying said patterned first metal layer wherein portions of said organic -- spin-on-glass layer within said via openings are exposed; vacuum baking said semiconductor substrate to remove moisture from said exposed portions of said organic -- spin-on-glass layer within said via openings; and thereafter exposing said organic spin-on-glass layer to nitrogen atoms at a vacuum of between about 4 to 8 Torr at a temperature of between about 350° to 450° C. for between about 10 to 50 seconds wherein said exposed portions of said organic spin-on-glass layer are converted to an inorganic material and wherein said inorganic material spin-on-glass layer prevents said outgassing from said intermetal dielectric layer to complete treatment of said intermetal dielectric layer in the fabrication of said integrated circuit.