US6556164B2
Expired / Lapsed
US
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Analog/digital converter and method for converting an analog input signal into a digital output signal
Assignee: Infineon Technologies AG
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Filing: 2002-07-29
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Granted: 2003-04-29
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Expires: 2022-07-29
Abstract
Abstract An analog-to-digital converter for successively and approximately converting an analog input signal into a digital output signal includes at least one comparator having a linear input module and an output module. The analog input signal is compared with a compare signal supplied by a digital-to-analog converter and supplies a comparator output signal for adjusting a clocked successive approximation register. The digital value temporarily stored in the successive approximation register is converted into the analog compare signal by the digital-to-analog converter. The inventive converter also includes an acceleration circuit supplying a reversible clock signal to the cocked successive approximation register according to at least one overload detector signal that detects overload of an appurtenant linear input module in the comparator.
Inventors
- 👤 Harald Schmid
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 09:52
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/46; H03M1/462
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
162 words
An analog/digital converter for successive approximation conversion of an analog input signal into a digital output signal, comprising: a clocked successive approximation register buffer storing a digital value; a digital/analog converter converting said digital value buffer-stored in said register to form an analog comparison signal, said digital/analog converter connected to said register and outputting said analog comparison signal; at least one comparator having: at least one linear input stage connected to said digital/analog converter; and an output stage; said at least one comparator: comparing the analog input signal with said analog comparison signal; outputting: a comparator output signal for setting said register; and at least one overdrive indicator signal; and indicating with said at least one overdrive indicator signal an overdriving of said at least one linear input stage; and an acceleration circuit connecting said at least one comparator to said register, said acceleration circuit outputting a switchable clock signal to said register based upon said at least one overdrive indicator signal.
Claim 2
Dependent Claim
162 words
An analog/digital converter for successive approximation conversion of an analog input signal into a digital output signal, comprising: a clocked successive approximation register buffer storing a digital value; a digital/analog converter converting said digital value buffer-stored in said register to form an analog comparison signal, said digital/analog converter connected to said register and outputting said analog comparison signal; at least one comparator having: at least one linear input stage connected to said digital/analog converter; and an output stage; said at least one comparator: comparing the analog input signal with said analog comparison signal; outputting: a comparator output signal for setting said register; and at least one overdrive indicator signal; and indicating with said at least one overdrive indicator signal an overdriving of said at least one linear input stage; and an acceleration circuit connecting said at least one comparator to said register, said acceleration circuit outputting a switchable clock signal to said register based upon said at least one overdrive indicator signal.
Claim 3
Dependent Claim
50 words
The analog/digital converter according to claim 1 , wherein: said at least one linear input stage is a plurality of linear input stages; and each of said linear input stages respectively have: a differential amplifier circuit; and an overdrive detection circuit for detecting an overdriving of said differential amplifier circuit.
Claim 4
Dependent Claim
18 words
The analog/digital converter according to claim 2 , wherein said overdrive detection circuit is a window discriminator circuit.
Claim 5
Dependent Claim
28 words
The analog/digital converter according to claim 2 , wherein said overdrive detection circuit detects a level and an arithmetic sign of an overdriving of said differential amplifier circuit.
Claim 6
Dependent Claim
17 words
The analog/digital converter according to claim 1 , including a clock generator connected to said acceleration circuit.
Claim 7
Dependent Claim
163 words
The analog/digital converter according to claim 1 , wherein: said comparator has a recovery time and a decision time; a controlled switching device is connected to said register; said acceleration circuit has: a pulse generator having an output and generating a pulse at said output; a first delay element delaying said pulse by a time corresponding to said recovery time of said comparator and outputting said delayed pulse at a first signal output, said first delay element connected to said output of said pulse generator; and a second delay element delaying said delayed pulse by a time corresponding to said decision time of said comparator, said second delay element connected to said first signal output and having a second signal output; said first signal output and said second signal output are connected to said switching device; and said switching device selectively connects said first signal output and said second signal output to said register based upon said at least one overdrive indicator signal.
Claim 8
Dependent Claim
15 words
The analog/digital converter according to claim 6 , wherein said switching device is a multiplexer.
Claim 9
Dependent Claim
34 words
The analog/digital converter according to claim 7 , wherein: said multiplexer has an output; said pulse generator is a D-type flip-flop; and said output of said multiplexer is fed back to said D-type flip-flop.
Claim 10
Dependent Claim
44 words
The analog/digital converter according to claim 7 , wherein: said multiplexer has an output, said pulse generator is a D-type flip-flop with at least one input; and said output of said multiplexer is connected to said at least one input of said D-type flip-flop.
Claim 11
Dependent Claim
16 words
The analog/digital converter according to claim 6 , wherein said pulse generator is a D-type flip-flop.
Claim 12
Dependent Claim
36 words
The analog/digital converter according to claim 6 , including a clock generator connected to said acceleration circuit, said pulse generator, said first delay element, and said second delay element being clocked synchronously by said clock generator.
Claim 13
Dependent Claim
107 words
The analog/digital converter according to claim 6 , wherein: said acceleration circuit switches said clock signal between: a first clock signal having a first clock period; and a second clock signal having a second clock period longer than said first clock period; said first clock period corresponds to said recovery time; said second clock period corresponds to said decision time; said first delay element and said second delay element are connected in series; said first delay element has a first delay equal to said first clock period; and said second delay element has a second delay equal to said first clock period and said second clock period.
Claim 14
Dependent Claim
42 words
The analog/digital converter according to claim 1 , wherein said acceleration circuit switches said clock signal between: a first clock signal having a first clock period; and a second clock signal having a second clock period longer than said first clock period.
Claim 15
Dependent Claim
42 words
The analog/digital converter according to claim 13 , wherein: said comparator has: a recovery time with respect to overdriving; and a decision time; said first clock period corresponds to said recovery time; and said second clock period corresponds to said decision time.
Claim 16
Dependent Claim
25 words
The analog/digital converter according to claim 1 , including a read register connected to said register for reading a digitized final value from said register.
Claim 17
Independent Claim
127 words
A method for converting an analog input signal into a digital output signal, which comprises: (a) comparing an analog comparison signal to the analog input signal with a comparator having a linear input stage, the analog comparison signal corresponding to a digital value buffer-stored in a clocked successive approximation register; (b) forming a comparator output signal based upon a result of the comparison to set the buffer-stored digital value in the register; (c) detecting if the linear input stage of the comparator is overdriven; and (d) switching a clock signal for the register to: a first clock signal having a given clock period if overdriving is detected; and a second clock signal having a clock period longer than the given clock period if no overdriving is detected.
Claim 18
Independent Claim
127 words
A method for converting an analog input signal into a digital output signal, which comprises: (a) comparing an analog comparison signal to the analog input signal with a comparator having a linear input stage, the analog comparison signal corresponding to a digital value buffer-stored in a clocked successive approximation register; (b) forming a comparator output signal based upon a result of the comparison to set the buffer-stored digital value in the register; (c) detecting if the linear input stage of the comparator is overdriven; and (d) switching a clock signal for the register to: a first clock signal having a given clock period if overdriving is detected; and a second clock signal having a clock period longer than the given clock period if no overdriving is detected.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-04-28 | 2006-10-28 | 2007-04-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-04-28 | 2010-10-28 | 2011-04-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-04-28 | 2014-10-28 | 2015-04-29 | $7700.00 | Window Closed / Lapsed |