US6154164A
Expired / Lapsed
US
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Variable clock rate analog-to-digital converter
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1998-09-16
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Granted: 2000-11-28
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Expires: 2018-09-16
Abstract
Abstract There is disclosed an integrated circuit including a successive approximation analog-to-digital converter. The successive approximation analog-to-digital converter can select which of at least two clock signals of different frequency drive the successive approximation converter for each bit determination. Each bit determination may employ a different clock frequency, or a particular clock frequency could be used for multiple bit determinations. The clock signals may be generated within the analog-to-digital converter, or the clock signal may be provided to the analog-to-digital converter.
Inventors
- 👤 George Francis Gross, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:15
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/46; H03M1/462
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
97 words
A method of converting an analog signal to a digital representation, comprising the steps of: sampling an analog signal to generate a sampled analog signal; providing the sampled analog signal to a successive approximation circuit; clocking the successive approximation circuit by a first clock having a first clock frequency to determine a first bit of a digital representation of the sampled analog signal; and clocking the successive approximation circuit by a second clock having a clock frequency different from the first clock frequency to determine a second bit of the digital representation of the sampled analog signal.
Claim 2
Independent Claim
97 words
A method of converting an analog signal to a digital representation, comprising the steps of: sampling an analog signal to generate a sampled analog signal; providing the sampled analog signal to a successive approximation circuit; clocking the successive approximation circuit by a first clock having a first clock frequency to determine a first bit of a digital representation of the sampled analog signal; and clocking the successive approximation circuit by a second clock having a clock frequency different from the first clock frequency to determine a second bit of the digital representation of the sampled analog signal.
Claim 3
Dependent Claim
17 words
The method of claim 1, wherein the second clock frequency is greater than the first clock frequency.
Claim 4
Independent Claim
74 words
A method of converting an analog signal to a multibit representation, comprising the steps of: sampling an analog signal to generate a sampled analog signal; providing the sampled analog signal to a successive approximation circuit; clocking the successive approximation circuit by a clock signal to determine each bit of the multibit representation; and changing the frequency of the clock signal applied to the successive approximation circuit between at least two of the bit determinations.
Claim 5
Independent Claim
74 words
A method of converting an analog signal to a multibit representation, comprising the steps of: sampling an analog signal to generate a sampled analog signal; providing the sampled analog signal to a successive approximation circuit; clocking the successive approximation circuit by a clock signal to determine each bit of the multibit representation; and changing the frequency of the clock signal applied to the successive approximation circuit between at least two of the bit determinations.
Claim 6
Dependent Claim
36 words
The method of claim 3, wherein the step of changing the frequency of the clock signal comprises changing the frequency of the clock signal applied to the successive approximation circuit between any two sequential bit determinations.
Claim 7
Dependent Claim
31 words
The method of claim 3, wherein the step of changing the frequency of the clock signal comprises increasing the frequency of the clock between at least two of the bit determinations.
Claim 8
Dependent Claim
101 words
An integrated circuit including an analog-to-digital converter, comprising: a clock generation circuit for generating a plurality of clock signals, each of the plurality of clock signals having a different frequency; a successive approximation circuit for determining bits of a digital representation of a sample of an analog signal input to the successive approximation circuit, the successive approximation circuit adapted to receive a clock signal from the clock generation circuit; and a selector circuit adapted to receive the plurality of clock signals from the clock generation circuit and to select one of the clock signals to provide to the successive approximation circuit.
Claim 9
Dependent Claim
101 words
An integrated circuit including an analog-to-digital converter, comprising: a clock generation circuit for generating a plurality of clock signals, each of the plurality of clock signals having a different frequency; a successive approximation circuit for determining bits of a digital representation of a sample of an analog signal input to the successive approximation circuit, the successive approximation circuit adapted to receive a clock signal from the clock generation circuit; and a selector circuit adapted to receive the plurality of clock signals from the clock generation circuit and to select one of the clock signals to provide to the successive approximation circuit.
Claim 10
Dependent Claim
27 words
An integrated circuit as recited in claim 6, wherein the selector circuit selects a clock signal in response to a signal received from the successive approximation circuit.
Claim 11
Dependent Claim
33 words
An integrated circuit as recited in claim 7, wherein the signal received by the selector circuit from the successive approximation circuit is indicative of the bit being determined by the successive approximation circuit.
Claim 12
Dependent Claim
17 words
An integrated circuit as recited in claim 6, wherein the integrated circuit is a digital signal processor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-28 | 2004-05-29 | 2004-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-28 | 2008-05-29 | 2008-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-28 | 2012-05-29 | 2012-11-28 | $7700.00 | Window Closed / Lapsed |