Analog to digital converter

Claim 2

In analog to digital data converter having means for applying an analog input signal, dual input analog signal comparator means having one input coupled to said input signal means, and successive approximation means including digital to analog conversion means providing an analog output coupled to the other input of said comparator means and digital circuit means coupled to the output of said analog signal comparator and being operable to generate a predetermined digital output corresponding to the difference between the analog input signal and said analog signal provided by said digital to analog conversion means, said digital output being coupled back to said digital to analog conversion means whereby the closest digital approximation of said analog input signal is generated by said digital circuit means, the improvement comprising: an externally controlled variable frequency binary clock pulse oscillator including circuit means coupling a clock pulse output to said digital circuit means; control circuit means comprising a strobe circuit coupled to said clock oscillator and including circuit means for receiving and counting said clock pulse output and generating binary control signals in accordance with the clock pulse count; circuit means coupling selected predetermined binary control signals from said strobe circuit to said digital circuit means for controlling the operation thereof; and circuit means coupling at least one binary control signal from said strobe circuit back to said variable frequency clock oscillator for changing the operating frequency of said clock oscillator after a predetermined pulse count as determined by said strobe circuit whereby said operating frequency of sAid clock oscillator starts at a predetermined value and later increases in order to reduce overall conversion time.

Claim 3

The converter as defined in claim 1 and additionally including: enabling means generating an enabling signal having a leading edge of a first binary logic sense; and a dual input logic gate having one input coupled to said enabling means, being responsive to said enabling signal and providing a binary output signal having a leading edge of a second binary logic sense; time delay means coupled to said logic gate; and variable time delay means in a feedback network coupled between said first recited time delay means and the other input of said logic gate providing a delayed signal thereto having a leading edge of said opposite binary logic sense wherein said logic gate then provides a binary output of said first binary logic sense.

Claim 4

The apparatus as defined by claim 2 wherein said enabling means comprises a flip-flop circuit.

Claim 5

The apparatus as defined by claim 2 wherein said logic gate comprises a NAND logic gate and said variable time delay means includes circuit means coupled to and responsive to said at least one control signal from said timing circuit means.

Claim 6

The apparatus as defined by claim 4 wherein said variable time delay means includes at least one switch controlled resistance-capacitance time delay network the time delay of which is determined by the RC time constant of said network; switch means operatively coupled to said time delay network and operated by another enabling signal; and a flip-flop circuit coupled to and operated by said at least one control signal from said control circuit means and being operative to produce said another enabling signal for operating said switch means.

Claim 7

The invention as defined by claim 3 wherein said variable time delay means includes at least two switch control resistance-capacitance time delay networks wherein the respective time delay is determined by the RC time constant of each network and first and second switch means operatively coupled respectively to said two time delay networks and controlled by respective flip-flop circuits responsive to control signals from said control circuit means for rendering said networks successively inoperative, thereby effecting a plurality of frequency changes of said oscillator.

Claim 8

The apparatus as defined by claim 6 and additionally including a first voltage amplifier, having a logic inversion, coupled between said networks and a second voltage amplifier, having a logic inversion coupled between the second time delay network and said other input of said logic gate.

Claim 9

The apparatus as defined by claim 7 wherein said first and second switch means comprise semiconductor switches.

Claim 10

The apparatus as defined by claim 8 wherein said semiconductor switches are comprised of FET switch devices.

Claim 11

In an analog to digital data converter having means for applying an analog input signal, dual input analog signal comparator means having one input coupled to said input signal means, and successive approximation means including digital to analog conversion means providing an analog output coupled to the other input of said comparator means and digital circuit means coupled to the output of said analog signal comparator and being operable to generate a predetermined digital output corresponding to the difference between the analog input signal and said analog signal provided by said digital to analog conversion means, said digital output being coupled back to said digital to analog conversion means whereby the closest digital approximation of said analog input signal is generated by said digital circuit means, the combination comprising: enabling means generating an enabling signal having a leading edge of a first binary logic sense; an externally controlled variable frequency clock oscillator including a. a dual input logic gate having one input coupled to said enabling means, being responsIve to said enabling signal and providing a binary output signal having a leading edge of a second binary logic sense, b. time delay means coupled to said logic gate, c. variable time delay means in a feedback network coupled between said first recited time delay means and the other input of said logic gate providing a delayed signal thereto having a leading edge of said opposite binary logic sense wherein said logic gate then provides a binary output of said first binary logic sense, and d. circuit means coupling a clock pulse output to said digital circuit means; control circuit means coupled to said clock oscillator and including circuit means for receiving and counting said clock pulse output and generating control signals in accordance with the clock pulse count; circuit means coupling selected predetermined control signals from said control circuit means to said digital circuit means for controlling the operation thereof; and circuit means coupling at least one control signal from said control circuit means back to said variable frequency clock oscillator for changing the operating frequency of said clock oscillator after a predetermined pulse count whereby said operating frequency of said clock oscillator starts at a predetermined value and later increases in order to reduce overall conversion time.

Claim 12

In an analog to digital data converter having means for applying an analog input signal, dual input analog signal comparator means having one input coupled to said input signal means, and successive approximation means including digital to analog conversion means providing an analog output coupled to the other input of said comparator means and digital circuit means coupled to the output of said analog signal comparator and being operable to generate a predetermined digital output corresponding to the difference between the analog input signal and said analog signal provided by said digital to analog conversion means, said digital output being coupled back to said digital to analog conversion means whereby the closest digital approximation of said analog input signal is generated by said digital circuit means, the combination comprising: enabling means generating an enabling signal having a leading edge of a first binary logic sense; an externally controlled variable frequency clock oscillator including a. a dual input logic gate having one input coupled to said enabling means, being responsIve to said enabling signal and providing a binary output signal having a leading edge of a second binary logic sense, b. time delay means coupled to said logic gate, c. variable time delay means in a feedback network coupled between said first recited time delay means and the other input of said logic gate providing a delayed signal thereto having a leading edge of said opposite binary logic sense wherein said logic gate then provides a binary output of said first binary logic sense, and d. circuit means coupling a clock pulse output to said digital circuit means; control circuit means coupled to said clock oscillator and including circuit means for receiving and counting said clock pulse output and generating control signals in accordance with the clock pulse count; circuit means coupling selected predetermined control signals from said control circuit means to said digital circuit means for controlling the operation thereof; and circuit means coupling at least one control signal from said control circuit means back to said variable frequency clock oscillator for changing the operating frequency of said clock oscillator after a predetermined pulse count whereby said operating frequency of said clock oscillator starts at a predetermined value and later increases in order to reduce overall conversion time.