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US6544835B2 Expired / Lapsed US ⏱️ 0.0 years remaining

Method of forming a ruthenium film by CVD

Assignee: Renesas Electronics Corp
•
Filing: 2002-06-18
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Granted: 2003-04-08
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Expires: 2022-06-18
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Abstract

Abstract There is provided a technique for forming an Ru film on the bottom of a deep hole with a considerable film thickness for the lower electrode of an information storage capacity element in order to improve the yield of manufacturing DRAMs. The Ru film is formed on the side wall and the bottom of a deep hole as material for preparing the lower electrode of an information storage capacity element to be produced there under the condition of a gasification flow rate ratio of the raw materials ((Ru(C 2 H 5 C 5 H 4 ) 2 /O 2 ) is not less than 10% Then, the ratio of the film thickness of the Ru film on the bottom “b” of the hole to the largest film thickness “a” of the Ru film in the hole is not less than 50%.

Inventors

  • 👤 Satoshi Yamamoto
  • 👤 Shinpei Iijima

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 02:47
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; C; C23; C23C; C23C16/00; C23C16/22; C23C16/30; C23C16/40; H10B12/30; H10B12/31; H10B12/315; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/042; H10D1/60; H10D1/68; H10D1/692; H10D1/694; H10D1/711; H10D1/716; H10P; H10P14/00; H10P14/40; H10P14/412; H10P14/42; H10P14/43; H10W20/071; H10W20/074; H10W20/076; H10W20/081; H10D1/682; H10W20/089

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 115 words
A process for manufacturing a semiconductor integrated circuit device, comprising: (a) forming an interlayer insulating film over a semiconductor substrate; (b) forming a hole in said interlayer insulating film; (c) forming a first electrically conductive film over a side wall and a bottom of said hole by reacting an organic compound of material of said first electrically conductive film and an oxidizing agent, a gasification flow rate of said organic compound of material of said first electrically conductive film being not less than 5% of a flow rate of the oxidizing agent; (d) forming an insulating film over said first electrically conductive film; and (e) forming a second electrically conductive film on said insulating film.
Claim 2
Dependent Claim 115 words
A process for manufacturing a semiconductor integrated circuit device, comprising: (a) forming an interlayer insulating film over a semiconductor substrate; (b) forming a hole in said interlayer insulating film; (c) forming a first electrically conductive film over a side wall and a bottom of said hole by reacting an organic compound of material of said first electrically conductive film and an oxidizing agent, a gasification flow rate of said organic compound of material of said first electrically conductive film being not less than 5% of a flow rate of the oxidizing agent; (d) forming an insulating film over said first electrically conductive film; and (e) forming a second electrically conductive film on said insulating film.
Claim 3
Dependent Claim 26 words
The method according to claim 1 , wherein a depth of said hole is not less than five times of a short diameter of said hole.
Claim 4
Dependent Claim 44 words
The method according to claim 1 , wherein a ratio of film thickness of the first electrically conductive film over the bottom of the hole to the largest film thickness of said first electrically conductive film in the hole is not less than 50%.
Claim 5
Dependent Claim 17 words
The method according to claim 1 , wherein said first electrically conductive film is made of Ru.
Claim 6
Dependent Claim 35 words
The method according to claim 1 , wherein reaction of the organic compound of material of said first electrically conductive film and the oxidizing agent is conducted at a temperature not higher than 300° C.

References Cited (Backward Citations)

US6057081A Cited
US5973351A Cited
US5977241A Cited
US6180482B1 Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2006-04-07 2006-10-07 2007-04-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2010-04-07 2010-10-07 2011-04-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2014-04-07 2014-10-07 2015-04-08 $7700.00 Window Closed / Lapsed

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