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US6535989B1
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Input clock delayed by a plurality of elements that are connected to logic circuitry to produce a clock frequency having a rational multiple less than one
Assignee: Hewlett Packard Development Co LP
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Filing: 1999-12-22
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Granted: 2003-03-18
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Expires: 2019-12-22
Abstract
Abstract An apparatus for producing one or more clock signals comprises a plurality of delay elements sequentially connected and logic circuitry connected to several of the plurality of delay elements. A clock signal fed through the plurality of delay elements produces multiple delayed versions of the clock signal. Logic circuitry selects and combines the delayed clock signal versions to produce one or more output clock signals, each having a frequency that is a selected fraction of the input clock signal. An associated method delays the input clock signal N times sequentially for a natural number N. then selects a series of time splices of the delayed clock signals to produce an output clock signal. In some implementations the input clock signal can be referenced to a reference clock signal. The output clock signal frequency can be set to (N/M)×f ref , for a natural number M and reference clock signal frequency f ref . The apparatus and associated method can flexibly produce a large variety of output clock frequencies and frequency ratios, lock to f ref with a dynamic response independent of the output frequency range and can be optimized to a single reference frequency, need not relock to change output frequency, and reduce clock skew.
Inventors
- 👤 Josef A Dvorak
- 👤 Ricky L Pettit
- 👤 David B Hollenbeck
- 👤 Kent R Townley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:47
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/15026; H03K5/1504; G; G06; G06F; G06F1/00; G06F1/04; G06F1/08; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0816; H03L7/099; H03L7/0995; H03L7/0996; H03L7/16
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
107 words
An apparatus comprising: a plurality of delay elements accepting, directly or indirectly, an input clock signal; and logic circuitry, connected to several of the plurality of delay elements and having an output, whereby the output is a clock signal having a frequency that is a rational multiple of the frequency of the input clock signal, wherein the rational multiple is less than one wherein the number of delay elements is N, and the frequency of the output clock signal is (N/M)×f REF , where M is a natural number, M>N, and f REF is the frequency of the clock signal fed through the plurality of delay elements.
Claim 2
Independent Claim
107 words
An apparatus comprising: a plurality of delay elements accepting, directly or indirectly, an input clock signal; and logic circuitry, connected to several of the plurality of delay elements and having an output, whereby the output is a clock signal having a frequency that is a rational multiple of the frequency of the input clock signal, wherein the rational multiple is less than one wherein the number of delay elements is N, and the frequency of the output clock signal is (N/M)×f REF , where M is a natural number, M>N, and f REF is the frequency of the clock signal fed through the plurality of delay elements.
Claim 3
Dependent Claim
14 words
The apparatus of claim 1 wherein the plurality of delay elements are sequentially connected.
Claim 4
Dependent Claim
17 words
The apparatus of claim 2 wherein each of the plurality of delay elements provides an equal delay.
Claim 5
Dependent Claim
17 words
The apparatus of claim 2 wherein the plurality of delay elements are directly connected in a loop.
Claim 6
Dependent Claim
70 words
The apparatus of claim 1 further comprising: a phase detector having at least two inputs and at least one output, a first of the inputs connected to one of the plurality of delay elements, a second of the inputs accepting a reference clock signal; and a feedback network, wherein the phase detector output is connected to the feedback network, so as to cause the first and second inputs to lock.
Claim 7
Dependent Claim
19 words
The apparatus of claim 5 wherein the phase detector and feedback network are part of a phase locked loop.
Claim 8
Dependent Claim
19 words
The apparatus of claim 5 wherein the phase detector and feedback network are part of a delay locked loop.
Claim 9
Dependent Claim
87 words
The apparatus of claim 1 wherein the logic circuitry comprises: a multiplexor having several signal inputs respectively connected to the several delay elements, having a port select input, and having an output; a state machine having a first output connected to the multiplexor port select input and having a second output; and a logic gate having a first input connected to the multiplexor output and a second input connected to the state machine second output, wherein the output of the logic gate is the output clock signal.
Claim 10
Dependent Claim
15 words
The apparatus of claim 8 wherein the logic gate is an edge sensitive AND gate.
Claim 11
Dependent Claim
27 words
The apparatus of claim 1 wherein the reference clock signal is a processor core clock signal and the output clock signal is an external bus clock signal.
Claim 12
Dependent Claim
19 words
The apparatus of claim 1 wherein the output clock signal is a binary clock signal of periodic rectangular pulses.
Claim 13
Dependent Claim
17 words
The apparatus of claim 1 wherein the output clock signal has a duty cycle less than 50%.
Claim 14
Independent Claim
82 words
A method comprising: delaying a clock signal N times, where N is a natural number, whereby a number of delayed clock signals are produced; selecting a series of time splices of the delayed clock signals, so as to produce an output clock signal; and locking the clock signal to a reference clock signal wherein the frequency of the output clock signal is (N/M)×f REF , where M is a natural number and f REF is the frequency of the reference clock signal.
Claim 15
Independent Claim
82 words
A method comprising: delaying a clock signal N times, where N is a natural number, whereby a number of delayed clock signals are produced; selecting a series of time splices of the delayed clock signals, so as to produce an output clock signal; and locking the clock signal to a reference clock signal wherein the frequency of the output clock signal is (N/M)×f REF , where M is a natural number and f REF is the frequency of the reference clock signal.
Claim 16
Dependent Claim
17 words
The method of claim 13 wherein the delaying step comprises delaying the clock signal N times sequentially.
Claim 17
Dependent Claim
12 words
The method of claim 13 wherein the locking step comprises phase locking.
Claim 18
Dependent Claim
12 words
The method of claim 13 wherein the locking step comprises delay locking.
Claim 19
Independent Claim
64 words
A method comprising: delaying a clock signal N times, where N is a natural number, whereby a number of delayed clock signals are produced; and selecting a series of time splices of the delayed clock signals, so as to produce an output clock signal wherein the series of time splices of the delayed clock signals is a repeating sequence based on a modulo-N ring.
Claim 20
Independent Claim
64 words
A method comprising: delaying a clock signal N times, where N is a natural number, whereby a number of delayed clock signals are produced; and selecting a series of time splices of the delayed clock signals, so as to produce an output clock signal wherein the series of time splices of the delayed clock signals is a repeating sequence based on a modulo-N ring.
Claim 21
Independent Claim
116 words
An apparatus comprising: a plurality of delay elements accepting, directly or indirectly, a reference clock signal f REF ; and logic circuitry, connected to one or more of the plurality of delay elements and having an output terminal, supplying a clock signal having a logic frequency that is a rational multiple (N/M) of the reference frequency f REF , the logic circuitry selecting signals from delay elements 1 to N for a selected frequency ratio in a repeated sequence that can be determined by an iterative algorithm as follows: Initialization: Y:=0; Output Y; Loop: Perform integer division (Y+M)/N→quotient Q and remainder R; Output (Q−1)X's, where X is a “don't care” state; Y:R; Output Y; Repeat loop.
Claim 22
Independent Claim
116 words
An apparatus comprising: a plurality of delay elements accepting, directly or indirectly, a reference clock signal f REF ; and logic circuitry, connected to one or more of the plurality of delay elements and having an output terminal, supplying a clock signal having a logic frequency that is a rational multiple (N/M) of the reference frequency f REF , the logic circuitry selecting signals from delay elements 1 to N for a selected frequency ratio in a repeated sequence that can be determined by an iterative algorithm as follows: Initialization: Y:=0; Output Y; Loop: Perform integer division (Y+M)/N→quotient Q and remainder R; Output (Q−1)X's, where X is a “don't care” state; Y:R; Output Y; Repeat loop.
Claim 23
Independent Claim
90 words
An apparatus comprising: a plurality of delay elements accepting, directly or indirectly, a reference clock signal f REF ; and means connected to several of the plurality of delay elements for generating an output timing signal as a selected combination of delayed reference clock signals, the output timing signal having a frequency that is a rational multiple of the frequency of the input clock signal, wherein for a number of delay elements N the frequency of the output clock signal is (N/M)×f REF , where M is a natural number.
Claim 24
Independent Claim
90 words
An apparatus comprising: a plurality of delay elements accepting, directly or indirectly, a reference clock signal f REF ; and means connected to several of the plurality of delay elements for generating an output timing signal as a selected combination of delayed reference clock signals, the output timing signal having a frequency that is a rational multiple of the frequency of the input clock signal, wherein for a number of delay elements N the frequency of the output clock signal is (N/M)×f REF , where M is a natural number.
Claim 25
Dependent Claim
23 words
An apparatus according to claim 19 wherein: the output timing signal frequency is less than the reference clock signal frequency f REF .
Claim 26
Dependent Claim
23 words
An apparatus according to claim 19 wherein: the output timing signal frequency is greater than the reference clock signal frequency f REF .
Claim 27
Dependent Claim
16 words
An apparatus according to claim 19 wherein: the apparatus generates a plurality of output timing signals.
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