US6157694A
Expired / Lapsed
US
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Fractional frequency divider
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1998-12-09
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Granted: 2000-12-05
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Expires: 2018-12-09
Abstract
Abstract In systems embodying the invention X clock signals having the same frequency, with each clock signal having a different phase, are supplied to the inputs of a multiplexer whose output is connected to the input of an "integer" frequency divider circuit; where X is an integer greater than 1. The mulitplexer is controlled to selectively supply different ones of the X clock signals to the frequency divider circuit for producing at the output of the frequency divider circuit a signal whose frequency is a function of the divider ratio of the frequency divider circuit and the sequencing of the clock signals supplied to the frequency divider circuit.
Inventors
- 👤 Patrik Larsson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 08:40
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/64; H03K23/68; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0995; H03L7/0996; H03L7/16; H03L7/18; H03L7/197; H03L7/1974
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
218 words
Apparatus comprising: a source of clock signals for producing X clock signals having the same frequency (f1) with each clock signal having a different phase; where X is an integer greater than 1; a frequency divider circuit having an input and an output; a multiplexer having an input port for receiving said X clock signals and having an output port for selectively coupling one of said X clock signals to said output port; and wherein the output port of the multiplexer is connected to the input of said frequency divider circuit; a selection circuit coupled to said source of clock signals and to the output of said frequency divider, said selection circuit being responsive to said X clock signals and to said output of said frequency divider circuit for producing a control signal and for applying the control signal to the multiplexer for controlling the sequence of the clock signals applied to the input of the frequency divider circuit, the selection circuit for selectively supplying a different one of said X clock signals to said frequency divider circuit and for producing at the output of the frequency divider circuit a signal whose frequency is a function of the divider ratio of the frequency divider circuit and the sequencing of the clock signals supplied to the frequency divider circuit.
Claim 2
Dependent Claim
218 words
Apparatus comprising: a source of clock signals for producing X clock signals having the same frequency (f1) with each clock signal having a different phase; where X is an integer greater than 1; a frequency divider circuit having an input and an output; a multiplexer having an input port for receiving said X clock signals and having an output port for selectively coupling one of said X clock signals to said output port; and wherein the output port of the multiplexer is connected to the input of said frequency divider circuit; a selection circuit coupled to said source of clock signals and to the output of said frequency divider, said selection circuit being responsive to said X clock signals and to said output of said frequency divider circuit for producing a control signal and for applying the control signal to the multiplexer for controlling the sequence of the clock signals applied to the input of the frequency divider circuit, the selection circuit for selectively supplying a different one of said X clock signals to said frequency divider circuit and for producing at the output of the frequency divider circuit a signal whose frequency is a function of the divider ratio of the frequency divider circuit and the sequencing of the clock signals supplied to the frequency divider circuit.
Claim 3
Dependent Claim
22 words
Apparatus as claimed in claim 1 wherein said selection circuit also includes circuitry for controlling the divider ratio of the frequency divider.
Claim 4
Dependent Claim
37 words
Apparatus as claimed in claim 2 wherein the frequency divider circuit is a programmable divider circuit and the control circuit is coupled to the frequency divider to supply control signals to it for controlling the divider ratio.
Claim 5
Dependent Claim
18 words
Apparatus as claimed in claim 1 wherein said source of clock signals is a voltage controlled oscillator (VCO).
Claim 6
Dependent Claim
24 words
Apparatus as claimed in claim 4 wherein said VCO includes a number of stages with the propagation delay of each stage being substantially equal.
Claim 7
Dependent Claim
19 words
Apparatus as claimed in claim 1 wherein said source of clock signals is a voltage controlled delay line (VCDL).
Claim 8
Dependent Claim
72 words
Apparatus as claimed in claim 1 wherein the application of the X clock signals to the frequency divider circuit are controlled to produce an output signal (fo) at the output of the frequency divider whose frequency is equal to [f1]/[N+(K/X)]; where f1 is the frequency of each one the clock signals and N is the divider ratio of the frequency divider circuit, and K may be any integer from 1 to (X-1).
Claim 9
Dependent Claim
29 words
Apparatus as claimed in claim 7 wherein each one of the X clock signals has a phase spacing relative to its adjacent clock signals which is equal to f1/X.
Claim 10
Dependent Claim
201 words
Apparatus comprising: a source of clock signals for producing X clock signals having the same frequency (f1) with each clock signal having a different phase; where X is an integer greater than 1; a frequency divider circuit; a selection circuit coupled between said source of clock signals and said frequency divider circuit for selectively supplying a different one of said X clock signals to said frequency divider circuit; wherein said selection circuit includes a multiplexer having an input port for receiving said X clock signals and having an output port for selectively coupling one of said X clock signals to said output port; and wherein the output port of the multiplexer is connected to an input of said frequency divider circuit; said selection circuit including circuitry for producing a control signal and for applying the control signal to the multiplexer for controlling the sequence of the clock signals applied to the frequency divider circuit; said selection circuit also including circuitry for controlling the divider ratio of the frequency divider; and wherein the frequency divider circuit is a programmable divider circuit and the selection circuit is coupled to the frequency divider to supply control signals to it for controlling the divider ratio.
Claim 11
Dependent Claim
201 words
Apparatus comprising: a source of clock signals for producing X clock signals having the same frequency (f1) with each clock signal having a different phase; where X is an integer greater than 1; a frequency divider circuit; a selection circuit coupled between said source of clock signals and said frequency divider circuit for selectively supplying a different one of said X clock signals to said frequency divider circuit; wherein said selection circuit includes a multiplexer having an input port for receiving said X clock signals and having an output port for selectively coupling one of said X clock signals to said output port; and wherein the output port of the multiplexer is connected to an input of said frequency divider circuit; said selection circuit including circuitry for producing a control signal and for applying the control signal to the multiplexer for controlling the sequence of the clock signals applied to the frequency divider circuit; said selection circuit also including circuitry for controlling the divider ratio of the frequency divider; and wherein the frequency divider circuit is a programmable divider circuit and the selection circuit is coupled to the frequency divider to supply control signals to it for controlling the divider ratio.
Claim 12
Dependent Claim
128 words
Apparatus comprising: a source of clock signals including a voltage controlled oscillator (VCO) for producing X clock signals having the same frequency (f1) with each clock signal having a different phase; where X is an integer greater than 1; a frequency divider circuit; a selection circuit coupled between said source of clock signals and said frequency divider circuit for selectively supplying a different one of said X clock signals to said frequency divider circuit; and wherein said selection circuit includes a multiplexer having an input port for receiving said X clock signals and having an output port for selectively coupling one of said X clock signals to said output port; and wherein the output port of the multiplexer is connected to an input of said frequency divider circuit.
Claim 13
Dependent Claim
128 words
Apparatus comprising: a source of clock signals including a voltage controlled oscillator (VCO) for producing X clock signals having the same frequency (f1) with each clock signal having a different phase; where X is an integer greater than 1; a frequency divider circuit; a selection circuit coupled between said source of clock signals and said frequency divider circuit for selectively supplying a different one of said X clock signals to said frequency divider circuit; and wherein said selection circuit includes a multiplexer having an input port for receiving said X clock signals and having an output port for selectively coupling one of said X clock signals to said output port; and wherein the output port of the multiplexer is connected to an input of said frequency divider circuit.
Claim 14
Dependent Claim
24 words
Apparatus as claimed in claim 10 wherein said VCO includes a number of stages with the propagation delay of each stage being substantially equal.
Claim 15
Dependent Claim
129 words
Apparatus comprising: a source of clock signals including a voltage controlled delay line (VCDL) for producing X clock signals having the same frequency (f1) with each clock signal having a different phase; where X is an integer greater than 1; a frequency divider circuit; a selection circuit coupled between said source of clock signals and said frequency divider circuit for selectively supplying a different one of said X clock signals to said frequency divider circuit; and wherein said selection circuit includes a multiplexer having an input port for receiving said X clock signals and having an output port for selectively coupling one of said X clock signals to said output port; and wherein the output port of the multiplexer is connected to an input of said frequency divider circuit.
Claim 16
Dependent Claim
129 words
Apparatus comprising: a source of clock signals including a voltage controlled delay line (VCDL) for producing X clock signals having the same frequency (f1) with each clock signal having a different phase; where X is an integer greater than 1; a frequency divider circuit; a selection circuit coupled between said source of clock signals and said frequency divider circuit for selectively supplying a different one of said X clock signals to said frequency divider circuit; and wherein said selection circuit includes a multiplexer having an input port for receiving said X clock signals and having an output port for selectively coupling one of said X clock signals to said output port; and wherein the output port of the multiplexer is connected to an input of said frequency divider circuit.
Claim 17
Dependent Claim
207 words
Apparatus comprising: a source of clock signals for producing X clock signals having the same frequency (f1) with each clock signal having a different phase; where X is an integer greater than 1; a frequency divider circuit; a selection circuit coupled between said source of clock signals and said frequency divider circuit for selectively supplying a different one of said X clock signals to said frequency divider circuit; wherein said selection circuit coupled between said source of clock signals and a frequency divider circuit for selectively supplying a different one of said X clock signals to said frequency divider circuit is for producing at the output of the frequency divider circuit a signal whose frequency is a function of the divider ratio of the frequency divider circuit and the sequencing of the clock signals supplied to the frequency divider circuit; and wherein the application of the X clock signals to the frequency divider circuit are controlled to produce an output signal (fo) at the output of the frequency divider whose frequency is equal to [f1]/[N+(K/X)]; where f1 is the frequency of each one the clock signals and N is the divider ratio of the frequency divider circuit, and K may be any integer from 1 to (X-1).
Claim 18
Dependent Claim
207 words
Apparatus comprising: a source of clock signals for producing X clock signals having the same frequency (f1) with each clock signal having a different phase; where X is an integer greater than 1; a frequency divider circuit; a selection circuit coupled between said source of clock signals and said frequency divider circuit for selectively supplying a different one of said X clock signals to said frequency divider circuit; wherein said selection circuit coupled between said source of clock signals and a frequency divider circuit for selectively supplying a different one of said X clock signals to said frequency divider circuit is for producing at the output of the frequency divider circuit a signal whose frequency is a function of the divider ratio of the frequency divider circuit and the sequencing of the clock signals supplied to the frequency divider circuit; and wherein the application of the X clock signals to the frequency divider circuit are controlled to produce an output signal (fo) at the output of the frequency divider whose frequency is equal to [f1]/[N+(K/X)]; where f1 is the frequency of each one the clock signals and N is the divider ratio of the frequency divider circuit, and K may be any integer from 1 to (X-1).
Claim 19
Dependent Claim
29 words
Apparatus as claimed in claim 13 wherein each one of the X clock signals has a phase spacing relative to its adjacent clock signals which is equal to f1/X.
Claim 20
Independent Claim
261 words
A method for producing a fractional division of a clock signal in a system in which a voltage controlled oscillator (VCO) produces X clock signals having the same frequency (f) but with different phases, where X is an integer greater than one (1), comprising the steps of: selectively selecting different ones of said X clock signals and applying the selected one of the X clock signals to a divide-by-N network for producing at its output an output frequency signal whose frequency is a function of the divide ratio of the divide-by-N network and the sequencing of the selected clock signals applied to the divider network; wherein the step of producing X clock signals having the same frequency (fo) but with different phases includes the step of producing these X clock signals with equal spacing between adjacent clock signals; wherein the step of producing X clock signals having the same frequency (fo) but with different phases includes the step of producing these X clock signals with substantially equal time delays between at least one of the rising and falling edges of adjacent clock signals; and wherein the step of selectively selecting different ones of said X clock signals and applying the selected one of the X clock signals to a divide-by-N network includes the steps of applying the X clock signals to an input port of a multiplexer and controlling the multiplexer for successively coupling different adjacent ones of the X clock signals to an output port of the multiplexer and then applying the output of the multiplexer to the divide-by-N network.
Claim 21
Independent Claim
261 words
A method for producing a fractional division of a clock signal in a system in which a voltage controlled oscillator (VCO) produces X clock signals having the same frequency (f) but with different phases, where X is an integer greater than one (1), comprising the steps of: selectively selecting different ones of said X clock signals and applying the selected one of the X clock signals to a divide-by-N network for producing at its output an output frequency signal whose frequency is a function of the divide ratio of the divide-by-N network and the sequencing of the selected clock signals applied to the divider network; wherein the step of producing X clock signals having the same frequency (fo) but with different phases includes the step of producing these X clock signals with equal spacing between adjacent clock signals; wherein the step of producing X clock signals having the same frequency (fo) but with different phases includes the step of producing these X clock signals with substantially equal time delays between at least one of the rising and falling edges of adjacent clock signals; and wherein the step of selectively selecting different ones of said X clock signals and applying the selected one of the X clock signals to a divide-by-N network includes the steps of applying the X clock signals to an input port of a multiplexer and controlling the multiplexer for successively coupling different adjacent ones of the X clock signals to an output port of the multiplexer and then applying the output of the multiplexer to the divide-by-N network.
References Cited (Backward Citations)
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Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-12-05 | 2004-06-05 | 2004-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-12-05 | 2008-06-05 | 2008-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-12-05 | 2012-06-05 | 2012-12-05 | $7700.00 | Window Closed / Lapsed |