Patent US6535043B2 successfully refreshed from Google Patents.
US6535043B2
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Clock signal selection system, method of generating a clock signal and programmable clock manager including same
Assignee: Lattice Semiconductor Corp
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Filing: 2001-05-23
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Granted: 2003-03-18
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Expires: 2021-05-23
Abstract
Abstract For use with a programmable clock manager (PCM), a selection system and method of generating a clock signal. In one embodiment, the selection system includes a phase selector, having multiple taps, configured to generate multiple phase shifted signals from a reference signal corresponding to an input signal with a fixed phase shift therebetween. The phase selector is further configured to select at least two of the phase shifted signals. The selection system further includes a duty cycle synthesis circuit configured to generate a clock signal having a duty cycle as a function of a phase shift between the selected phase shifted signals.
Inventors
- 👤 Minhan Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:02
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H; H03; H03K; H03K19/00; H03K19/0175; H03K19/017581; H03K19/02; H03K19/173; H03K19/177; H03K19/17724; H03K19/17732; H03K19/17736; H03K19/1774; H03K19/17744; H03K19/17748; H03K19/1776; H03K19/1778; H03K19/17788; H03K19/17792; H03K5/00; H03K5/13; H03K5/133; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0995; H03L7/0996; H03L7/081
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
89 words
A selection system for use with a programmable clock manager (PCM) having an input signal, comprising: a phase selector, having multiple taps, configured to generate corresponding multiple phase shifted signals from a reference signal corresponding to said input signal with a fixed phase shift therebetween, said phase selector further configured to select at least two of said phase shifted signals; and a duty cycle synthesis circuit configured to generate a clock signal having a duty cycle as a function of a phase shift between said selected phase shifted signals.
Claim 2
Dependent Claim
89 words
A selection system for use with a programmable clock manager (PCM) having an input signal, comprising: a phase selector, having multiple taps, configured to generate corresponding multiple phase shifted signals from a reference signal corresponding to said input signal with a fixed phase shift therebetween, said phase selector further configured to select at least two of said phase shifted signals; and a duty cycle synthesis circuit configured to generate a clock signal having a duty cycle as a function of a phase shift between said selected phase shifted signals.
Claim 3
Dependent Claim
19 words
The selection system as recited in claim 1 wherein said phase selector comprises a voltage-controlled oscillator and a multiplexer.
Claim 4
Dependent Claim
23 words
The selection system as recited in claim 1 wherein said phase selector comprises a multi-tap fully differential voltage-controlled oscillator and a programmable multiplexer.
Claim 5
Dependent Claim
27 words
The selection system as recited in claim 1 wherein said phase selector comprises eight taps and said phase shifted signals have a 45 degree phase shift therebetween.
Claim 6
Dependent Claim
23 words
The selection system as recited in claim 1 further comprising a delay compensation circuit configured to create a delay in said reference signal.
Claim 7
Dependent Claim
32 words
The selection system as recited in claim 1 wherein said phase selector is further configured to modify a frequency of said phase shifted signals based on a frequency of said reference signal.
Claim 8
Dependent Claim
40 words
The selection system as recited in claim 1 wherein said phase selector is further configured to modify a frequency of said phase shifted signals based on a frequency of said reference signal from about 10 MHz to about 100 MHz.
Claim 9
Independent Claim
54 words
A method of generating a clock signal, comprising: developing multiple phase shifted signals, having a fixed phase shift therebetween, from a reference signal; selecting at least two of said phase shifted signals; and generating said clock signal having a duty cycle as a function of a phase shift between said selected phase shifted signals.
Claim 10
Independent Claim
54 words
A method of generating a clock signal, comprising: developing multiple phase shifted signals, having a fixed phase shift therebetween, from a reference signal; selecting at least two of said phase shifted signals; and generating said clock signal having a duty cycle as a function of a phase shift between said selected phase shifted signals.
Claim 11
Dependent Claim
24 words
The method as recited in claim 8 wherein said developing is performed by a voltage-controlled oscillator and said selecting is performed by a multiplexer.
Claim 12
Dependent Claim
27 words
The method as recited in claim 8 said developing is performed by a multi-tap fully differential voltage-controlled oscillator and said selecting is performed by a programmable multiplexer.
Claim 13
Dependent Claim
19 words
The method as recited in claim 8 wherein said phase shifted signals have a 45 degree phase shift therebetween.
Claim 14
Dependent Claim
16 words
The method as recited in claim 8 further comprising creating a delay in said reference signal.
Claim 15
Dependent Claim
25 words
The method as recited in claim 8 further comprising modifying a frequency of said phase shifted signals based on a frequency of said reference signal.
Claim 16
Dependent Claim
27 words
The method as recited in claim 13 wherein said modifying includes modifying a frequency of said phase shifted signals from about 10 MHz to about 100 MHz.
Claim 17
Dependent Claim
112 words
A programmable clock manager (PCM), comprising: a comparator circuit configured to determine whether a frequency and a phase of a feedback signal are substantially equal to a frequency and a phase of an input signal; and a selection system, comprising: a phase selector, having multiple taps, configured to generate multiple phase shifted signals from a reference signal corresponding to said input signal with a fixed phase shift therebetween, said phase selector further configured to select at least two of said phase shifted signals, and a duty cycle synthesis circuit configured to generate a clock signal having a duty cycle as a function of a phase shift between said selected phase shifted signals.
Claim 18
Dependent Claim
112 words
A programmable clock manager (PCM), comprising: a comparator circuit configured to determine whether a frequency and a phase of a feedback signal are substantially equal to a frequency and a phase of an input signal; and a selection system, comprising: a phase selector, having multiple taps, configured to generate multiple phase shifted signals from a reference signal corresponding to said input signal with a fixed phase shift therebetween, said phase selector further configured to select at least two of said phase shifted signals, and a duty cycle synthesis circuit configured to generate a clock signal having a duty cycle as a function of a phase shift between said selected phase shifted signals.
Claim 19
Dependent Claim
21 words
The PCM as recited in claim 15 wherein said comparator circuit comprises a signal divider and a phase and frequency detector.
Claim 20
Dependent Claim
18 words
The PCM as recited in claim 15 wherein said phase selector comprises a voltage-controlled oscillator and a multiplexer.
Claim 21
Dependent Claim
26 words
The PCM as recited in claim 15 wherein said phase selector comprises eight taps and said phase shifted signals have a 45 degree phase shift therebetween.
Claim 22
Dependent Claim
26 words
The PCM as recited in claim 15 wherein said selection system further comprises a delay compensation circuit configured to create a delay in said reference signal.
Claim 23
Dependent Claim
31 words
The PCM as recited in claim 15 wherein said phase selector is further configured to modify a frequency of said phase shifted signals based on a frequency of said reference signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-03-17 | 2006-09-16 | 2007-03-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-03-17 | 2010-09-16 | 2011-03-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-03-17 | 2014-09-16 | 2015-03-18 | $7700.00 | Window Closed / Lapsed |