Apparatus and method for manufacturing a semiconductor device

Claim 2

A semiconductor device having a wiring structure in which at least one wiring layer including a wiring and an insulating film surrounding the wiring and having a substantially flat upper surface is formed above a substrate, wherein the insulating film of the at least one wiring layer has one of a carbon concentration and a metal oxide concentration, one of which differs in a film thickness direction.

Claim 3

A semiconductor device having a multilayer wiring structure in which a plurality of wiring layers each including a wiring and an insulating film surrounding the wiring and having a substantially flat upper surface are formed and layered above a substrate, wherein the insulating film of at least one of the plurality of wiring layers has one of a carbon concentration and a metal oxide concentration, one of which is different from one of a carbon concentration and a metal oxide concentration of the insulating film of another one of the plurality of wiring layers.

Claim 4

A semiconductor device having a multilayer wiring structure in which a plurality of wiring layers each including a wiring and an insulating film surrounding the wiring and having a substantially flat upper surface are formed and layered above a substrate, wherein the insulating film of at least one of the plurality of wiring layers has one of a carbon concentration and a metal oxide concentration, one of which is different from one of a carbon concentration and a metal oxide concentration of the insulating film of another one of the plurality of wiring layers.

Claim 5

A semiconductor device according to claim 2 , wherein the insulating film of the at least one of the plurality of wiring layers has one of a carbon concentration and a metal oxide concentration, one of which differs in a film thickness direction.

Claim 6

A semiconductor device comprising: a first wiring layer including a first insulating film and a plurality of wirings formed with the first insulating film interposed therebetween; a plug formed to make contact with the wiring; a second insulating film formed on the first wiring layer so as to cover a side portion of the plug; a third insulating film formed on the second insulating film, having a carbon concentration lower than that of the second insulating film, and having a groove portion which is formed so as to expose the plug; and a second wiring layer which is formed in the groove portion.

Claim 7

A semiconductor device comprising: a first wiring layer including a first insulating film and a plurality of wirings formed with the first insulating film interposed therebetween; a plug formed to make contact with the wiring; a second insulating film formed on the first wiring layer so as to cover a side portion of the plug; a third insulating film formed on the second insulating film, having a carbon concentration lower than that of the second insulating film, and having a groove portion which is formed so as to expose the plug; and a second wiring layer which is formed in the groove portion.

Claim 8

A semiconductor device comprising: a multilayer wiring structure comprising at least two wiring layers which are formed above a substrate and each of which has a plurality of wirings and an inter-wiring insulating film interposed therebetween, wherein the inter-wiring insulating film of at least one of the at least two wiring layers includes a first inter-wiring insulating film which comprises at least one of an FSG film, a TEOS film, and a USG film, a second inter-wiring insulating film which is formed on the first inter-wiring insulating film and which comprises at least one of an organic insulating film and a silica-based porous film, and a third inter-wiring insulating film which is formed on the second inter-wiring insulating film and which comprises at least one of a TEOS film and a USG film, upper surfaces of the first, second, and third inter-wiring insulating films are substantially flat, the first and second inter-wiring insulating films differ from each other in at least one of the film stress acting in a direction substantially parallel to the upper surfaces of the first and second inter-wiring insulating films and film hardness, and the second and third inter-wiring insulating films differ from each other in at least one of film stress acting in a direction substantially parallel to the upper surfaces of the second and third inter-wiring insulating films and film hardness; and an inter-layer insulating film which is interposed between the at least two wiring layers and which is formed above the substrate.

Claim 9

A semiconductor device comprising: a multilayer wiring structure comprising at least two wiring layers which are formed above a substrate and each of which has a plurality of wirings and an inter-wiring insulating film interposed therebetween, wherein the inter-wiring insulating film of at least one of the at least two wiring layers includes a first inter-wiring insulating film which comprises at least one of an FSG film, a TEOS film, and a USG film, a second inter-wiring insulating film which is formed on the first inter-wiring insulating film and which comprises at least one of an organic insulating film and a silica-based porous film, and a third inter-wiring insulating film which is formed on the second inter-wiring insulating film and which comprises at least one of a TEOS film and a USG film, upper surfaces of the first, second, and third inter-wiring insulating films are substantially flat, the first and second inter-wiring insulating films differ from each other in at least one of the film stress acting in a direction substantially parallel to the upper surfaces of the first and second inter-wiring insulating films and film hardness, and the second and third inter-wiring insulating films differ from each other in at least one of film stress acting in a direction substantially parallel to the upper surfaces of the second and third inter-wiring insulating films and film hardness; and an inter-layer insulating film which is interposed between the at least two wiring layers and which is formed above the substrate.

Claim 10

A semiconductor device according to claim 5 , wherein the at least one of the at least two wiring layers including the first, second, and third inter-wiring insulating films is formed in an uppermost layer among the at least two wiring layers.

Claim 11

A semiconductor device according to claim 5 , wherein the at least one of the at least two wiring layers including the first, second, and third inter-wiring insulating films is formed in two uppermost layers among the at least two wiring layers.

Claim 12

A semiconductor device comprising: a multi-layer wiring structure comprising at least two wiring layer which are formed above a substrate and each of which has a plurality of wirings and an inter-wiring insulating film interposed therebetween, wherein the inter-wiring insulating film of at least one of the at least two wiring layers includes a first inter-wiring insulating film which comprises at least one of an FSG film, a TEOS film, and a USG film, a second inter-wiring insulating film which is formed on the first inter-wiring insulating film and which comprises at least one of an organic insulating film and a silica-based porous film, and a third inter-wiring insulating film which is formed on the second inter-wiring insulating film and which comprises at least one of a TEOS film and a USG film, upper surfaces of the first, second, and third inter-wiring insulating films are substantially flat, the first and second inter-wiring insulating films differ from each other in film stress acting in a direction substantially parallel to the upper surfaces of the first and second inter-wiring insulating films, and the second and third inter-wiring insulating films differ from each other in film stress acting in a direction substantially parallel to the upper surfaces of the second and third inter-wiring insulating films; and an inter-layer insulating film which is interposed between the at least two wiring layers and which is formed above the substrate.

Claim 13

A semiconductor device comprising: a multi-layer wiring structure comprising at least two wiring layer which are formed above a substrate and each of which has a plurality of wirings and an inter-wiring insulating film interposed therebetween, wherein the inter-wiring insulating film of at least one of the at least two wiring layers includes a first inter-wiring insulating film which comprises at least one of an FSG film, a TEOS film, and a USG film, a second inter-wiring insulating film which is formed on the first inter-wiring insulating film and which comprises at least one of an organic insulating film and a silica-based porous film, and a third inter-wiring insulating film which is formed on the second inter-wiring insulating film and which comprises at least one of a TEOS film and a USG film, upper surfaces of the first, second, and third inter-wiring insulating films are substantially flat, the first and second inter-wiring insulating films differ from each other in film stress acting in a direction substantially parallel to the upper surfaces of the first and second inter-wiring insulating films, and the second and third inter-wiring insulating films differ from each other in film stress acting in a direction substantially parallel to the upper surfaces of the second and third inter-wiring insulating films; and an inter-layer insulating film which is interposed between the at least two wiring layers and which is formed above the substrate.

Claim 14

A semiconductor device according to claim 5 , wherein a direction in which a film stress of the first inter-wiring insulating film acts differs from a direction in which a film stress of the second inter-wiring insulating film acts, and the direction in which the film stress of the second inter-wiring insulating film acts differs from a direction in which a film stress of the third inter-wiring insulating film acts.

Claim 15

A semiconductor device according to claim 5 , wherein film stresses of the first, second, and third inter-wiring insulating films act in a same direction.

Claim 16

A semiconductor device according to claim 5 , wherein film hardness of the first and third inter-wiring insulating films are higher than film hardness of the second inter-wiring insulating film.

Claim 17

A semiconductor device according to claim 5 , wherein the second inter-wiring insulating film has a relative dielectric constant of 3 or less.

Claim 18

A semiconductor device according to claim 8 , wherein a direction in which a film stress of the first inter-wiring insulating film acts differs from a direction in which a film stress of the second inter-wiring insulating film acts, and the direction in which the film stress of the second inter-wiring insulating film acts differs from a direction in which a film stress of the third inter-wiring insulating film acts.

Claim 19

A semiconductor device according to claim 8 , wherein film stresses of the first, second, and third inter-wiring insulating films act in a same direction.

Claim 20

A semiconductor device according to claim 8 , wherein film hardnesses of the first and third inter-wiring insulating films are higher than a hardness of the second inter-wiring insulating film.

Claim 21

A semiconductor device according to claim 8 , wherein the second inter-wiring insulating film has a relative dielectric constant of 3 or less.

Claim 22

A semiconductor device according to claim 5 , wherein the first inter-wiring insulating film is an FSG film, and the third inter-wiring insulating film comprises at least one of a TEOS film and a USG film.

Claim 23

A semiconductor device according to claim 8 , wherein the first inter-wiring insulating film is an FSG film, and the third inter-wiring insulating film comprises at least one of a TEOS film and a USG film.