Patent US6531324B2 successfully refreshed from Google Patents.
US6531324B2
Expired / Lapsed
US
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MFOS memory transistor & method of fabricating same
Assignee: Sharp Laboratories of America Inc
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Filing: 2001-03-28
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Granted: 2003-03-11
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Expires: 2021-03-28
Abstract
Abstract A ferroelectric transistor gate structure with a ferroelectric gate and passivation sidewalls is provided. The passivation sidewalls serve as an insulator to reduce, or eliminate, the diffusion of oxygen or hydrogen into the ferroelectric gate. A method of forming the ferroelectric gate structure is also provided. The method comprises the steps of forming a sacrificial gate structure, removing the sacrificial gate structure, depositing passivation insulator material, etching the passivation insulator material using anisotropic plasma etching to form passivation sidewalls, depositing a ferroelectric material, polishing the ferroelectric material using CMP, and forming a top electrode overlying the ferroelectric material.
Inventors
- 👤 Sheng Teng Hsu
- 👤 Fengyan Zhang
- 👤 Tingkai Li
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:08
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/689; H10D30/701; H10D64/01; H10D64/031; H10D64/033
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
111 words
A method of forming a ferroelectric transistor structure on a substrate comprising the steps of: a) forming a gate insulator over the substrate; b) producing a sacrificial gate structure overlying the substrate; c) removing the sacrificial gate structure to form a gate opening having a depth; d) depositing a passivation insulator over the substrate; e) etching the passivation insulator using anisotropic etching, whereby passivation sidewalls are formed; f) depositing a ferroelectric material over the substrate to a thickness greater than the depth of the gate opening; g) polishing the ferroelectric material using chemical-mechanical polishing (CMP), whereby a ferroelectric gate is formed; and h) forming a top electrode overlying the ferroelectric gate.
Claim 2
Independent Claim
111 words
A method of forming a ferroelectric transistor structure on a substrate comprising the steps of: a) forming a gate insulator over the substrate; b) producing a sacrificial gate structure overlying the substrate; c) removing the sacrificial gate structure to form a gate opening having a depth; d) depositing a passivation insulator over the substrate; e) etching the passivation insulator using anisotropic etching, whereby passivation sidewalls are formed; f) depositing a ferroelectric material over the substrate to a thickness greater than the depth of the gate opening; g) polishing the ferroelectric material using chemical-mechanical polishing (CMP), whereby a ferroelectric gate is formed; and h) forming a top electrode overlying the ferroelectric gate.
Claim 3
Dependent Claim
53 words
The method of claim 1 , wherein the step of forming the sacrificial gate accomplished by the steps of: a) depositing and patterning a layer of sacrificial gate material, whereby a sacrificial gate is formed; b) forming an oxide overlying the sacrificial gate; c) and polishing the oxide to expose the sacrificial gate.
Claim 4
Dependent Claim
18 words
The method of claim 2 , wherein the layer of sacrificial gate material is silicon nitride or polysilicon.
Claim 5
Dependent Claim
17 words
The method of claim 2 , wherein the step of polishing is accomplished using chemical-mechanical polishing (CMP).
Claim 6
Dependent Claim
26 words
The method of claim 1 , wherein the step of depositing the gate insulator is accomplished by chemical vapor deposition (CVD), pulsed CVD, sputtering, or evaporation.
Claim 7
Dependent Claim
36 words
The method of claim 1 , wherein the step of depositing the gate insulator deposits ZrO 2 , zirconium silicate, Zr—Al—Si—O, HfO 2 , hafnium silicate, Hf—Al—O, La—Al—O, lanthanum oxide or Ta 2 O 5 .
Claim 8
Dependent Claim
26 words
The method of claim 1 , wherein the step of depositing the ferroelectric material is accomplished by metal-organic chemical vapor deposition (MOCVD), or chemical-solution deposition (CSD).
Claim 9
Dependent Claim
29 words
The method of claim 1 , wherein the step of depositing the ferroelectric material deposits PGO, PZT, SBT, SBO, SBTO, SBTN, STO, BTO, BLT, LNO or YMnO 3 .
Claim 10
Dependent Claim
18 words
The method of claim 1 , wherein the top electrode is iridium, platinum, iridium oxide or platinum oxide.
Claim 11
Dependent Claim
24 words
The method of claim 1 , wherein the step of forming the top electrode is accomplished by depositing and patterning a top electrode layer.
Claim 12
Dependent Claim
21 words
The method of claim 1 , wherein the step of forming the top electrode is accomplished by using a damascene process.
Claim 13
Dependent Claim
32 words
The method of claim 1 , wherein the step of depositing the passivation insulator deposits TiO 2 , Al 2 O 3 , TiAlO x , or Si 3 N 4 .
Claim 14
Dependent Claim
20 words
The method of claim 1 , wherein the step of etching the passivation insulator is accomplished using anisotropic plasma etch.
Claim 15
Dependent Claim
31 words
The method of claim 1 , wherein the step of depositing the gate insulator deposits ZrO 2 , zirconium silicate, Zr—Al—Si—O, HfO 2 , hafnium silicate, Hf—Al—O, La—Al—O, or lanthanum oxide.
Claim 16
Dependent Claim
25 words
The method of claim 1 , wherein the step of depositing the ferroelectric material deposits PGO, SBTN, STO, BTO, BLT, LNO or YMnO 3 .
Claim 17
Dependent Claim
27 words
The method of claim 1 , wherein the step of depositing the passivation insulator deposits TiO 2 , Al 2 O 3 , or TiAlO x .
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| 3.5 Years (Year 4) | 2006-03-10 | 2006-09-09 | 2007-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-03-10 | 2010-09-09 | 2011-03-11 | $3760.00 | Window Closed / Lapsed |
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