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US6524913B1
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Method of fabricating a non-volatile memory with a spacer
Assignee: MARCRONIX INTERNATIONAL Co Ltd
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Filing: 2001-12-04
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Granted: 2003-02-25
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Expires: 2021-12-04
Abstract
Abstract A method of fabricating a non-volatile memory, in which a charge-trapping layer consisting of insulating materials and bar-like conductive layers to be patterned into the gates are formed at first. The buried bit-lines are formed in the substrate between the bar-like conductive layers. Each of the buried bit-lines extends into the substrate under a portion of an adjacent high-K spacer, but not to the substrate under an adjacent bar-like conductive layer. High-K spacers are formed on the side-walls of the bar-like conductive layers. Then the bar-like conductive layers are patterned into the gates, and word-lines are formed on the substrate to electrically connect with the gates. The material of the high-K spacer has a dielectric constant and the high-K spacer has a width, such that a channel will extend to the substrate under the high-K spacer and connect with the buried bit-line when the non-volatile memory is operated.
Inventors
- 👤 Hung-Sui Lin
- 👤 Han-Chao Lai
- 👤 Tao-Cheng Lu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:37
CPC Classifications
H; H10; H10B; H10B43/00; H10B43/30; H10B69/00; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0413; H10D30/60; H10D30/69; H10D64/00; H10D64/01; H10D64/031; H10D64/037
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
157 words
A method of fabricating a non-volatile memory, comprising the steps of: providing a substrate; forming a charge-trapping layer on the substrate; forming a plurality of bar-like conductive layers on the charge-trapping layer; forming a plurality of buried bit-lines in the substrate between the bar-like conductive layers; forming a plurality of high-K spacers on the side-walls of the bar-like conductive layers; forming a plurality of gates on the bar-like conductive layers; and forming a plurality of word-lines over the substrate to electrically connect with the gates, wherein each of the buried bit-lines extends into the substrate under a portion of an adjacent high-K spacer, but not to the substrate under an adjacent bar-like conductive layer; and a material of the high-K spacer has a dielectric constant and the high-K spacer has a width, such that a channel will extend to the substrate under the high-K spacer and connect with the buried bit-line when the non-volatile memory is operated.
Claim 2
Independent Claim
157 words
A method of fabricating a non-volatile memory, comprising the steps of: providing a substrate; forming a charge-trapping layer on the substrate; forming a plurality of bar-like conductive layers on the charge-trapping layer; forming a plurality of buried bit-lines in the substrate between the bar-like conductive layers; forming a plurality of high-K spacers on the side-walls of the bar-like conductive layers; forming a plurality of gates on the bar-like conductive layers; and forming a plurality of word-lines over the substrate to electrically connect with the gates, wherein each of the buried bit-lines extends into the substrate under a portion of an adjacent high-K spacer, but not to the substrate under an adjacent bar-like conductive layer; and a material of the high-K spacer has a dielectric constant and the high-K spacer has a width, such that a channel will extend to the substrate under the high-K spacer and connect with the buried bit-line when the non-volatile memory is operated.
Claim 3
Dependent Claim
15 words
The method of claim 1 , wherein the dielectric constant is substantially larger than 30.
Claim 4
Dependent Claim
35 words
The method of claim 1 , wherein each of the buried bit-lines extends into the substrate under a portion of an adjacent high-K spacer, but not to the substrate under an adjacent bar-like conductive layer.
Claim 5
Dependent Claim
30 words
The method of claim 1 , wherein the charge-trapping layer comprises, from bottom to top, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.
Claim 6
Dependent Claim
59 words
The method of claim 1 , wherein the method of forming the buried bit-lines comprises the steps of: forming a plurality of sacrificial spacers on the side-walls of the bar-like conductive layers; performing an ion implantation to form the buried bit-lines by using the bar-like conductive layers and the sacrificial spacers as a mask; and removing the sacrificial spacers.
Claim 7
Dependent Claim
50 words
The method of claim 5 , further comprising removing the second silicon oxide layer exposed by the bar-like conductive layers while removing the sacrificial spacers, and wherein the charge-trapping layer comprises, from bottom to top, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.
Claim 8
Dependent Claim
18 words
The method of claim 5 , wherein the sacrificial spacers are made of silicon oxide or silicon nitride.
Claim 9
Dependent Claim
30 words
The method of claim 5 , wherein a width of each sacrificial spacer is less than that of each high-K spacer, and the ion implantation is a vertical ion implantation.
Claim 10
Dependent Claim
32 words
The method of claim 5 , wherein a width of each sacrificial spacer is substantially the same as that of each high-K spacer; and the ion implantation is a tilt ion implantation.
Claim 11
Dependent Claim
19 words
The method of claim 1 , wherein a material of the high-K spacers comprises Ta 2 O 5 .
Claim 12
Dependent Claim
57 words
The method of claim 1 , wherein the method the forming the gates and the word-lines comprises the steps of: patterning the bar-like conductive layer into the gates; filling a plurality of gaps between the gates and between the high-K spacers with a dielectric material; and forming the word-lines electrically connecting with the gates over the substrate.
Claim 13
Dependent Claim
64 words
The method of claim 1 , wherein the method of forming the gates and the word-lines comprises the steps of: filling a plurality of gaps between the high-K spacers with a dielectric material; forming a conductive layer on the bar-like conductive layers and the dielectric material; and patterning the conductive layer into the word-lines and successively patterning the bar-like conductive layers into the gates.
Claim 14
Independent Claim
206 words
A method of fabricating a non-volatile memory, comprising the steps of: providing a substrate; forming a charge-trapping layer on the substrate, wherein the charge-trapping layer comprises, from bottom to top, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer; forming a plurality of bar-like conductive layers on the second silicon oxide layer; forming a plurality of sacrificial spacers on the side-walls of the bar-like conductive layers; performing an ion implantation to form a plurality of buried bit-lines in the substrate between the bar-like conductive layers by using the bar-like conductive layers and the sacrificial spacers as a mask; removing the sacrificial spacers; forming a plurality of high-K spacers on the side-walls of the bar-like conductive layers; forming a plurality of gates on the bar-like conductive layers; filling a plurality of gaps between the gates and between the high-K spacers with a dielectric material; and forming a plurality of word-lines electrically connecting with the gates over the substrate, wherein a material of the high-K spacer has a dielectric constant and the high-K spacer has a width, such that a channel will extend to the substrate under the high-K spacer and connect with the buried bit-line when the non-volatile memory is operated.
Claim 15
Independent Claim
206 words
A method of fabricating a non-volatile memory, comprising the steps of: providing a substrate; forming a charge-trapping layer on the substrate, wherein the charge-trapping layer comprises, from bottom to top, a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer; forming a plurality of bar-like conductive layers on the second silicon oxide layer; forming a plurality of sacrificial spacers on the side-walls of the bar-like conductive layers; performing an ion implantation to form a plurality of buried bit-lines in the substrate between the bar-like conductive layers by using the bar-like conductive layers and the sacrificial spacers as a mask; removing the sacrificial spacers; forming a plurality of high-K spacers on the side-walls of the bar-like conductive layers; forming a plurality of gates on the bar-like conductive layers; filling a plurality of gaps between the gates and between the high-K spacers with a dielectric material; and forming a plurality of word-lines electrically connecting with the gates over the substrate, wherein a material of the high-K spacer has a dielectric constant and the high-K spacer has a width, such that a channel will extend to the substrate under the high-K spacer and connect with the buried bit-line when the non-volatile memory is operated.
Claim 16
Dependent Claim
15 words
The method of claim 13 , wherein the dielectric constant is substantially larger than 30.
Claim 17
Dependent Claim
35 words
The method of claim 13 , wherein each of the buried bit-lines extends into the substrate under a portion of an adjacent high-K spacer, but not to the substrate under an adjacent bar-like conductive layer.
Claim 18
Dependent Claim
30 words
The method of claim 13 , wherein a width of each sacrificial spacer is less than that of each high-K spacer; and the ion implantation is a vertical ion implantation.
Claim 19
Dependent Claim
32 words
The method of claim 13 , wherein a width of each sacrificial spacer is substantially the same as that of each high-K spacer; and the ion implantation is a tilt ion implantation.
Claim 20
Dependent Claim
39 words
The method of claim 13 , wherein the material of the sacrificial spacers is silicon oxide, and the second silicon oxide layer exposed by the bar-like conductive layers is also removed in the step of removing the sacrificial spacers.
Claim 21
Dependent Claim
27 words
The method of claim 1 , further comprising performing an annealing step after forming a plurality of buried bit-lines in the substrate between the bar-like conductive layers.
Claim 22
Dependent Claim
27 words
The method of claim 13 , further comprising performing an annealing step after forming a plurality of buried bit-lines in the substrate between the bar-like conductive layers.
References Cited (Backward Citations)
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