US6465303B1
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Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory
Assignee: Longitude Flash Memory Solutions Ltd
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Filing: 2001-06-20
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Granted: 2002-10-15
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Expires: 2021-06-20
Abstract
Abstract One aspect of the present invention relates to a method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, involving the steps of providing a semiconductor substrate having a core region and periphery region, the core region containing SONOS type memory cells and the periphery region containing gate transistors; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; forming a spacer material over the semiconductor substrate; masking the core region and forming spacers adjacent the gate transistors in the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.
Inventors
- 👤 Mark T. Ramsbey
- 👤 Narbeh Derhacobian
- 👤 Janet Wang
- 👤 Angela Hui
- 👤 Tuan Pham
- 👤 Ravi Sunkavalli
- 👤 Mark Randolph
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:22
CPC Classifications
H; H10; H10B; H10B43/00; H10B43/30; H10B43/40
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
97 words
A method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, comprising: providing a semiconductor substrate having a core region and periphery region, the core region comprising SONOS type memory cells and the periphery region comprising gate transistors; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; forming a spacer material over the semiconductor substrate; masking the core region and forming spacers adjacent the gate transistors in the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.
Claim 2
Independent Claim
97 words
A method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, comprising: providing a semiconductor substrate having a core region and periphery region, the core region comprising SONOS type memory cells and the periphery region comprising gate transistors; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; forming a spacer material over the semiconductor substrate; masking the core region and forming spacers adjacent the gate transistors in the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.
Claim 3
Dependent Claim
25 words
The method according to claim 1 , wherein the spacer material comprises silicon dioxide, silicon nitride, silicon oxynitride, tetraethylorthosilicate, borophosphotetraethylorthosilicate, phosphosilicate glass, or borophosphosilicate glass.
Claim 4
Dependent Claim
18 words
The method according to claim 1 , wherein the spacer material is formed by chemical vapor deposition techniques.
Claim 5
Dependent Claim
23 words
The method according to claim 1 , wherein the spacers adjacent the gate transistors in the periphery region are formed by anisotropic etching.
Claim 6
Dependent Claim
35 words
The method according to claim 1 , wherein the first implant is implanted at a first dosage into the periphery region and the second implant is implanted at a second dosage into the periphery region.
Claim 7
Dependent Claim
21 words
The method according to claim 1 , wherein the spacer material encapsulates the SONOS type memory cells and the gate transistors.
Claim 8
Independent Claim
128 words
A method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, comprising: providing a semiconductor substrate having a core region and periphery region, the core region comprising SONOS type memory cells and the periphery region comprising gate transistors, the SONOS type memory cells comprising a charge trapping dielectric and a poly layer; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; depositing a spacer material over the semiconductor substrate in a substantially conformal manner; masking the core region and forming spacers adjacent the gate transistors in the periphery region by etching a portion of the spacer material over the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.
Claim 9
Independent Claim
128 words
A method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, comprising: providing a semiconductor substrate having a core region and periphery region, the core region comprising SONOS type memory cells and the periphery region comprising gate transistors, the SONOS type memory cells comprising a charge trapping dielectric and a poly layer; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; depositing a spacer material over the semiconductor substrate in a substantially conformal manner; masking the core region and forming spacers adjacent the gate transistors in the periphery region by etching a portion of the spacer material over the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.
Claim 10
Dependent Claim
25 words
The method according to claim 7 , wherein the spacer material comprises silicon dioxide, silicon nitride, silicon oxynitride, tetraethylorthosilicate, borophosphotetraethylorthosilicate, phosphosilicate glass, or borophosphosilicate glass.
Claim 11
Dependent Claim
17 words
The method according to claim 7 , wherein the spacer material is deposited by chemical vapor deposition.
Claim 12
Dependent Claim
23 words
The method according to claim 7 , wherein the spacers adjacent the gate transistors in the periphery region are formed by anisotropic etching.
Claim 13
Dependent Claim
23 words
The method according to claim 7 , wherein the first and second implants independently comprise at least one of arsenic, boron, and phosphorus.
Claim 14
Dependent Claim
35 words
The method according to claim 7 , wherein the first implant is implanted at a first dosage into the periphery region and the second implant is implanted at a second dosage into the periphery region.
Claim 15
Dependent Claim
17 words
The method according to claim 12 , wherein the second dosage is greater than the first dosage.
Claim 16
Dependent Claim
66 words
The method according to claim 7 , wherein the charge trapping dielectric comprises one of an ONO trilayer dielectric, an oxide/nitride bilayer dielectric, a nitride/oxide bilayer dielectric, an oxide/tantalum oxide bilayer dielectric, an oxide/tantalum oxide/oxide trilayer dielectric, an oxide/strontium titanate bilayer dielectric, an oxide/barium strontium titanate bilayer dielectric, an oxide/strontium titanate/oxide trilayer dielectric, an oxide/strontium titanate/barium strontium titanate trilayer dielectric, and an oxide/hafnium oxide/oxide trilayer dielectric.
Claim 17
Independent Claim
159 words
A method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, comprising: providing a semiconductor substrate having a core region and periphery region, the core region comprising SONOS type memory cells and the periphery region comprising gate transistors, the SONOS type memory cells comprising a charge trapping dielectric and a poly layer; implanting a first implant into the core region to form buried bit lines in the substrate adjacent the SONOS type memory cells and a first implant into the periphery region to form lightly doped regions in the substrate adjacent the gate transistors; depositing a spacer material over the semiconductor substrate in a substantially conformal manner; masking the core region and forming spacers adjacent the gate transistors in the periphery region by etching a portion of the spacer material over the periphery region; and implanting a second implant into the periphery region to form heavily doped regions in the substrate adjacent the lightly doped regions.
Claim 18
Independent Claim
159 words
A method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, comprising: providing a semiconductor substrate having a core region and periphery region, the core region comprising SONOS type memory cells and the periphery region comprising gate transistors, the SONOS type memory cells comprising a charge trapping dielectric and a poly layer; implanting a first implant into the core region to form buried bit lines in the substrate adjacent the SONOS type memory cells and a first implant into the periphery region to form lightly doped regions in the substrate adjacent the gate transistors; depositing a spacer material over the semiconductor substrate in a substantially conformal manner; masking the core region and forming spacers adjacent the gate transistors in the periphery region by etching a portion of the spacer material over the periphery region; and implanting a second implant into the periphery region to form heavily doped regions in the substrate adjacent the lightly doped regions.
Claim 19
Dependent Claim
25 words
The method according to claim 15 , wherein the spacer material comprises silicon dioxide, silicon nitride, silicon oxynitride, tetraethylorthosilicate, borophosphotetraethylorthosilicate, phosphosilicate glass, or borophosphosilicate glass.
Claim 20
Dependent Claim
25 words
The method according to claim 15 , wherein etching the portion of the spacer material over the periphery region is conducted in an anisotropic manner.
Claim 21
Dependent Claim
66 words
The method according to claim 15 , wherein the charge trapping dielectric comprises one of an ONO trilayer dielectric, an oxide/nitride bilayer dielectric, a nitride/oxide bilayer dielectric, an oxide/tantalum oxide bilayer dielectric, an oxide/tantalum oxide/oxide trilayer dielectric, an oxide/strontium titanate bilayer dielectric, an oxide/barium strontium titanate bilayer dielectric, an oxide/strontium titanate/oxide trilayer dielectric, an oxide/strontium titanate/barium strontium titanate trilayer dielectric, and an oxide/hafnium oxide/oxide trilayer dielectric.
Claim 22
Dependent Claim
31 words
The method according to claim 15 , wherein the charge trapping dielectric comprises an ONO dielectric comprising at least one of a nitrided oxide layer and a silicon-rich silicon nitride layer.
Claim 23
Dependent Claim
23 words
The method according to claim 15 , wherein the first and second implants independently comprise at least one of arsenic, boron, and phosphorus.
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