Patent US6495442B1 successfully refreshed from Google Patents.
US6495442B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Post passivation interconnection schemes on top of the IC chips
Assignee: Megica Corp
•
Filing: 2000-10-18
•
Granted: 2002-12-17
•
Expires: 2020-10-18
Abstract
Abstract A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
Inventors
- 👤 Mou-Shiung Lin
- 👤 Jin-Yuan Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:09
CPC Classifications
H; H10; H10W; H10W42/00; H10W42/60; H10W20/00; H10W20/01; H10W20/031; H10W20/071; H10W20/40; H10W20/41; H10W20/427; H10W20/435; H10W20/45; H10W20/47; H10W20/48; H10W20/495; H10W20/496; H10W20/497; H10W42/80; H10W72/00; H10W72/90; H10D; H10D89/00; H10D89/60
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
145 words
A method of forming a post passivation interconnection, comprising: forming one or more internal circuits comprising one or more active devices in and on a semiconductor substrate; forming one or more ESD circuits formed in and on said semiconductor substrate; a fine line metallization system, over said semiconductor substrate in one or more thin layers of dielectric; depositing a passivation layer over said fine line metallization system; forming a thick, wide metallization system above said passivation layer, in one or more thick layers of dielectric, wherein said thick layers of dielectric are thicker than said thin layers of dielectric, wherein said thick, wide metallization system is used as a distribution network for an electrical stimulus, and wherein said thick, wide metallization system is connected to said one or more ESD circuits, said one or more internal circuits, and to at least one off-chip contact pin.
Claim 2
Independent Claim
145 words
A method of forming a post passivation interconnection, comprising: forming one or more internal circuits comprising one or more active devices in and on a semiconductor substrate; forming one or more ESD circuits formed in and on said semiconductor substrate; a fine line metallization system, over said semiconductor substrate in one or more thin layers of dielectric; depositing a passivation layer over said fine line metallization system; forming a thick, wide metallization system above said passivation layer, in one or more thick layers of dielectric, wherein said thick layers of dielectric are thicker than said thin layers of dielectric, wherein said thick, wide metallization system is used as a distribution network for an electrical stimulus, and wherein said thick, wide metallization system is connected to said one or more ESD circuits, said one or more internal circuits, and to at least one off-chip contact pin.
Claim 3
Dependent Claim
51 words
The method of claim 1 wherein said distribution network is connected to said ESD circuits and to said one or more internal circuits by vias, which are formed through said one or more thick layers of dielectric, through said passivation layer, and through said one or more thin layers of dielectric.
Claim 4
Dependent Claim
15 words
The method of claim 2 wherein said electrical stimulus comprises a power or ground voltage.
Claim 5
Dependent Claim
24 words
The method of claim 3 wherein said ESD circuit is connected in parallel with said one or more internal circuits, through said distribution network.
Claim 6
Dependent Claim
38 words
The method of claim 3 wherein said distribution network acts as a global distribution for said power or ground voltages, and said vias are further connected to local power/ground distribution networks formed in said fine line metallization system.
Claim 7
Dependent Claim
15 words
The method of claim 2 wherein said electrical stimulus comprises a clock or signal voltage.
Claim 8
Dependent Claim
28 words
The method of claim 6 , further comprising connecting driver, receiver or I/O circuits in series between said one or more off-chip contact pins and said distribution network.
Claim 9
Dependent Claim
24 words
The method of claim 7 wherein said ESD circuit is connected in parallel with said driver, receiver or I/O circuits, through said distribution network.
Claim 10
Dependent Claim
38 words
The method of claim 6 wherein said distribution network acts as a global distribution for said clock or signal voltages, and said vias are further connected to local clock/signal distribution networks formed in said fine line metallization system.
Claim 11
Dependent Claim
24 words
The method of claim 1 wherein metal in said thick, wide metallization system is formed to a thickness of greater than about 1 micrometer.
Claim 12
Dependent Claim
26 words
The method of claim 1 wherein said one or more thick layers of dielectric is each formed to a thickness of greater than about 2 micrometers.
Claim 13
Independent Claim
145 words
A method of forming a post passivation interconnection, comprising: forming one or more internal circuits comprising one or more active devices in and on a semiconductor substrate; forming one or more ESD circuits in and on said semiconductor substrate; forming a fine line metallization system over said semiconductor substrate in one or more thin layers of dielectric; depositing a passivation layer over said fine line metallization system; forming a thick, wide metallization system above said passivation layer, in one or more thick layers of dielectric, wherein said thick layers of dielectric are thicker than said thin layers of dielectric, wherein said thick, wide metallization system is used as a power or ground distribution network for a power or ground input, respectively, and wherein said thick, wide metallization system is connected to said one or more internal circuits, and to at least one off-chip contact pin.
Claim 14
Independent Claim
145 words
A method of forming a post passivation interconnection, comprising: forming one or more internal circuits comprising one or more active devices in and on a semiconductor substrate; forming one or more ESD circuits in and on said semiconductor substrate; forming a fine line metallization system over said semiconductor substrate in one or more thin layers of dielectric; depositing a passivation layer over said fine line metallization system; forming a thick, wide metallization system above said passivation layer, in one or more thick layers of dielectric, wherein said thick layers of dielectric are thicker than said thin layers of dielectric, wherein said thick, wide metallization system is used as a power or ground distribution network for a power or ground input, respectively, and wherein said thick, wide metallization system is connected to said one or more internal circuits, and to at least one off-chip contact pin.
Claim 15
Dependent Claim
34 words
The method of claim 12 further comprising forming one or more ESD circuits, in and on said semiconductor substrate, connected to said distribution network, and in parallel with said one or more internal circuits.
Claim 16
Dependent Claim
51 words
The method of claim 13 wherein said distribution network is connected to said ESD circuits and to said one or more internal circuits by vias, which are formed through said one or more thick layers of dielectric, through said passivation layer, and through said one or more thin layers of dielectric.
Claim 17
Dependent Claim
38 words
The method of claim 12 wherein said distribution network acts as a global distribution for said power or ground inputs, and said vias are further connected to local power/ground distribution networks formed in said fine line metallization system.
Claim 18
Dependent Claim
20 words
The method of claim 13 wherein there is one or more ESD circuit formed for each said off-chip contact pin.
Claim 19
Dependent Claim
24 words
The method of claim 12 wherein metal in said thick, wide metallization system is formed to a thickness of greater than about 1 micrometer.
Claim 20
Dependent Claim
26 words
The method of claim 12 wherein said one or more thick layers of dielectric is each formed to a thickness of greater than about 2 micrometers.
Claim 21
Independent Claim
121 words
A method of forming a post passivation interconnection, comprising: forming one or more internal circuits comprising one or more active devices in and on a semiconductor substrate; forming a fine line metallization system, over said semiconductor substrate in one or more thin layers of dielectric; depositing a passivation layer over said fine line metallization system; forming a thick, wide metallization system above said passivation layer, in one or more thick layers of dielectric, wherein said thick layers of dielectric are thicker than said thin layers of dielectric, wherein said thick, wide metallization system is used as a distribution network for a clock or signal voltage, and wherein said thick, wide metallization system is connected to said one or more internal circuits.
Claim 22
Independent Claim
121 words
A method of forming a post passivation interconnection, comprising: forming one or more internal circuits comprising one or more active devices in and on a semiconductor substrate; forming a fine line metallization system, over said semiconductor substrate in one or more thin layers of dielectric; depositing a passivation layer over said fine line metallization system; forming a thick, wide metallization system above said passivation layer, in one or more thick layers of dielectric, wherein said thick layers of dielectric are thicker than said thin layers of dielectric, wherein said thick, wide metallization system is used as a distribution network for a clock or signal voltage, and wherein said thick, wide metallization system is connected to said one or more internal circuits.
Claim 23
Dependent Claim
46 words
The method of claim 19 wherein said distribution network is connected to said one or more internal circuits by vias, which are formed through said one or more thick layers of dielectric, through said passivation layer, and through said one or more thin layers of dielectric.
Claim 24
Dependent Claim
41 words
The method of claim 20 wherein said distribution network acts as a global distribution for said clock or signal voltages, and said vias are further connected to local clock or signal distribution networks, respectively, formed in said fine line metallization system.
Claim 25
Dependent Claim
24 words
The method of claim 19 wherein metal in said thick, wide metallization system is formed to a thickness of greater than about 1 micrometer.
Claim 26
Dependent Claim
25 words
The method of claim 19 wherein said one or more thick layers of dielectric are each formed to a thickness greater than about 2 micrometers.
References Cited (Backward Citations)
US5055907A
Cited
US5106461A
Cited
US5212403A
Cited
US5501006A
Cited
US5635767A
Cited
US5686764A
Cited
US6303423B1
Cited
US6180426B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-12-16 | 2006-06-17 | 2006-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-12-16 | 2010-06-17 | 2010-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-12-16 | 2014-06-17 | 2014-12-17 | $7700.00 | Window Closed / Lapsed |