Flip chip package with reduced number of package layers

Claim 2

A flip chip comprising: a semiconductor die; and a substrate, the substrate comprising: a first conductive layer bonded to said semiconductor die, said first conductive layer having a plurality of I/O signal traces and first voltage supply traces of a respective first polarity arranged in a repeating pattern of adjacent traces, each pattern including N I/O traces adjacent to one another and a first voltage supply trace; a dielectric layer having a first side and a second side, the first side affixed to said first conductive layer; and a second conductive layer aligned below said first conductive layer and affixed to the second dielectric layer side, said second conductive layer having a plurality of I/O signal traces and second voltage supply traces of respective second polarity, the I/O traces and second voltage supply traces of said second conductive layer being arranged in a repeating pattern of adjacent traces, each pattern including N I/O traces adjacent to one another and a second voltage supply trace; wherein: in plan view of said substrate at least a portion of each one of the first voltage supply traces of said first conductive layer is parallel and congruent with at least a portion of the I/O traces of said second conductive layer, and at least a portion of each of the second voltage supply traces of said second conductive layer is parallel and congruent with at least a portion of the I/O traces of said first conductive layer.

Claim 3

The flip chip defined in claim 1 wherein: said substrate is free of a dedicated power plane and further is free of a dedicated ground plane.

Claim 4

The flip chip defined in claim 1 wherein: the number of signal I/O traces in each pattern is represented by the number "N", and N is two with said portion of the I/O traces of each group each having a selected width and being spaced apart by a certain dimension; and the congruent and parallel portion of each voltage supply trace is substantially twice as wide as the I/O traces plus the certain dimension.

Claim 5

The flip chip defined in claim 3 wherein: said substrate is free of a dedicated power plane and further is free of a dedicated ground plane.

Claim 6

A substrate for coupling at least one semiconductor die to a mother board, the substrate comprising: a substantially planar dielectric layer having a first side and a second side; a first conductive layer mounted to the first side of said dielectric layer, said first conductive layer having a plurality of signal traces and a plurality of first voltage supply traces; a second conductive layer mounted to the second side of said dielectric layer, said second conductive layer having a plurality of signal traces and a plurality of second voltage supply traces; a plurality of die contacts on said first conductive layer for contacting said at least one semiconductor die; and a plurality of mother board lands on said second conductive layer for contacting said mother board; each of said first conductive layer and said second conductive layer including a respective repeating pattern of adjacent traces, each pattern including N signal traces adjacent to one another and said signal traces also being adjacent to a voltage supply trace of the pattern: wherein: in plan view of said substrate at least a portion of each one of the first and second voltage supply traces of each said first conductive layer and said second conductive layer individually is of a certain width and is parallel and congruent with at least a portion of all of the respective signal traces of a pattern of the other of said first conductive layer and second conductive layer, each said at least a portion of all of the respective signal traces of a pattern of the first conductive layer and second conductive layer cooperatively having a selected width including the individual widths of each signal trace portion as well as spacings therebetween, which selected width is substantially equal to the certain width of the parallel and congruent portion of a voltage supply trace.

Claim 7

A substrate for coupling at least one semiconductor die to a mother board, the substrate comprising: a substantially planar dielectric layer having a first side and a second side; a first conductive layer mounted to the first side of said dielectric layer, said first conductive layer having a plurality of signal traces and a plurality of first voltage supply traces; a second conductive layer mounted to the second side of said dielectric layer, said second conductive layer having a plurality of signal traces and a plurality of second voltage supply traces; a plurality of die contacts on said first conductive layer for contacting said at least one semiconductor die; and a plurality of mother board lands on said second conductive layer for contacting said mother board; each of said first conductive layer and said second conductive layer including a respective repeating pattern of adjacent traces, each pattern including N signal traces adjacent to one another and said signal traces also being adjacent to a voltage supply trace of the pattern: wherein: in plan view of said substrate at least a portion of each one of the first and second voltage supply traces of each said first conductive layer and said second conductive layer individually is of a certain width and is parallel and congruent with at least a portion of all of the respective signal traces of a pattern of the other of said first conductive layer and second conductive layer, each said at least a portion of all of the respective signal traces of a pattern of the first conductive layer and second conductive layer cooperatively having a selected width including the individual widths of each signal trace portion as well as spacings therebetween, which selected width is substantially equal to the certain width of the parallel and congruent portion of a voltage supply trace.

Claim 8

The substrate defined in claim 5, wherein: traces on said first conductive layer are arranged in repeating patterns of N signal traces between and substantially parallel at said at least a portion of each to at least a portion of said first voltage supply traces; and traces on said second conductive layer are arranged in repeating patterns of M signal traces between and substantially parallel at said at least a portion of each to at least a portion of said second voltage supply traces.

Claim 9

The substrate defined in claim 6, wherein: M equals N.

Claim 10

The substrate defined in claim 7, wherein: N is two.

Claim 11

The substrate defined in claim 7, wherein: N is three.

Claim 12

The substrate defined in claim 6, wherein: N does not equal M.

Claim 13

The substrate defined in claim 8, wherein: the first voltage supply traces are wider than the signal traces of said second conductive layer, and the second voltage supply traces are wider than the signal traces of the first conductive layer.

Claim 14

The substrate defined in claim 11 wherein: the first voltage supply traces are approximately twice as wide as the signal traces of said second conductive layer, and the second voltage supply traces are approximately twice as wide as the signal traces of the first conductive layer.

Claim 15

The substrate defined in claim 5, further comprising: at least one semiconductor die bonded to said first conductive layer.

Claim 16

A flip chip comprising: an integrated circuit die: and a substrate, the substrate comprising: a dielectric layer having a first side and a second side; and a first conductive layer having a die side and a bottom side, said first conductive layer having a plurality of voltage supply traces and a plurality of I/O signal traces, said integrated circuit die being affixed to the die side, said dielectric layer being affixed to the bottom side; said substrate further comprising: a second conductive layer having a dielectric side and a mother board side, said second conductive layer having a plurality of voltage supply traces and a plurality of I/O signal traces, said dielectric layer being affixed to the dielectric side; wherein: the mother board side of said second conductive layer is adapted for connection to a mother board; wherein: said first conductive layer includes plural repeating patterns each of two spaced apart I/O signal traces each having a respective width and adjacent to a voltage supply trace, said voltage supply traces of said first conductive layer being wider than said first conductive layer I/O signal traces; and said second conductive layer includes plural repeating patterns each of two spaced apart I/O signal traces each having a certain width and adjacent to a a voltage supply trace, said voltage supply traces of said second conductive layer being wider than said second conductive layer I/O signal traces; each of said voltage supply traces of each of said first conductive layer and of said second conductive layer having in plan view of said substrate a portion which is substantially parallel and congruent with a respective portion of said I/O signal traces of the other of said first conductive layer and said second conductive layer.

Claim 17

A flip chip comprising: an integrated circuit die: and a substrate, the substrate comprising: a dielectric layer having a first side and a second side; and a first conductive layer having a die side and a bottom side, said first conductive layer having a plurality of voltage supply traces and a plurality of I/O signal traces, said integrated circuit die being affixed to the die side, said dielectric layer being affixed to the bottom side; said substrate further comprising: a second conductive layer having a dielectric side and a mother board side, said second conductive layer having a plurality of voltage supply traces and a plurality of I/O signal traces, said dielectric layer being affixed to the dielectric side; wherein: the mother board side of said second conductive layer is adapted for connection to a mother board; wherein: said first conductive layer includes plural repeating patterns each of two spaced apart I/O signal traces each having a respective width and adjacent to a voltage supply trace, said voltage supply traces of said first conductive layer being wider than said first conductive layer I/O signal traces; and said second conductive layer includes plural repeating patterns each of two spaced apart I/O signal traces each having a certain width and adjacent to a a voltage supply trace, said voltage supply traces of said second conductive layer being wider than said second conductive layer I/O signal traces; each of said voltage supply traces of each of said first conductive layer and of said second conductive layer having in plan view of said substrate a portion which is substantially parallel and congruent with a respective portion of said I/O signal traces of the other of said first conductive layer and said second conductive layer.

Claim 18

The flip chip defined in claim 14 wherein: said first conductive layer includes a combined number of I/O and voltage supply traces that is approximately equal to the combined number of I/O and voltage supply traces on said second conductive layer.

Claim 19

The flip chip defined in claim 14 wherein: said first conductive layer includes a plurality of bump contacts for connecting to said die, said bump contacts being spaced approximately 200 to 250 microns apart; and said second conductive layer includes a plurality of lands for connecting to a mother board, said lands being spaced approximately 1 to 1.27 millimeters apart.

Claim 20

The flip chip defined in claim 15 wherein: said substrate is free of a dedicated power plane and further is free of a dedicated ground plane.

Claim 21

A flip chip assembly comprising: a semiconductor die having a plurality of die contact pads for electrical interface of I/O signals power with said die, and; a substrate having a first side and a second side, said substrate carrying said semiconductor die on said first side and providing electrical interface of said die contact pads with a plurality of substrate contacts presented on said second side; said substrate including: a first conductive layer affixed to said first side and electrically interfacing with die contact pads of said semiconductor die, said first conductive layer having a plurality of respective I/O signal traces and power supply traces arranged in plural repeating patterns of adjacent traces; a second conductive layer affixed to said second side, said second conductive layer also having a plurality of respective I/O signal traces and power supply traces arranged in a repeating pattern of adjacent traces; each repeating pattern of said first conductive layer and of said second conductive layer including a selected number of I/O traces each adjacent to at least one other I/O trace of that pattern, and a power supply trace adjacent to the selected number of I/O traces of that pattern, in a respective portion of each pattern each I/O trace having a selected width and being spaced from adjacent traces of that pattern by a certain dimension and cooperatively defining a total width for the I/O traces of that pattern in said respective portion; and in plan view of said substrate said power supply traces of each of said first conductive layer and of said second conductive layer also having a respective portion thereof with a width substantially equal to said total width of a congruent portion of said I/O traces in a pattern on the opposite side of said substrate, and where congruent with one another said portions of said I/O traces and of said power supply traces on opposite sides of said substrate also being mutually parallel.

Claim 22

A flip chip assembly comprising: a semiconductor die having a plurality of die contact pads for electrical interface of I/O signals power with said die, and; a substrate having a first side and a second side, said substrate carrying said semiconductor die on said first side and providing electrical interface of said die contact pads with a plurality of substrate contacts presented on said second side; said substrate including: a first conductive layer affixed to said first side and electrically interfacing with die contact pads of said semiconductor die, said first conductive layer having a plurality of respective I/O signal traces and power supply traces arranged in plural repeating patterns of adjacent traces; a second conductive layer affixed to said second side, said second conductive layer also having a plurality of respective I/O signal traces and power supply traces arranged in a repeating pattern of adjacent traces; each repeating pattern of said first conductive layer and of said second conductive layer including a selected number of I/O traces each adjacent to at least one other I/O trace of that pattern, and a power supply trace adjacent to the selected number of I/O traces of that pattern, in a respective portion of each pattern each I/O trace having a selected width and being spaced from adjacent traces of that pattern by a certain dimension and cooperatively defining a total width for the I/O traces of that pattern in said respective portion; and in plan view of said substrate said power supply traces of each of said first conductive layer and of said second conductive layer also having a respective portion thereof with a width substantially equal to said total width of a congruent portion of said I/O traces in a pattern on the opposite side of said substrate, and where congruent with one another said portions of said I/O traces and of said power supply traces on opposite sides of said substrate also being mutually parallel.