Active bias circuit

Claim 2

An active bias circuit connected to a power amplifier, comprising: first and second current mirror circuits connected to the power amplifier for maintaining a DC quiescent current to the power amplifier at a generally fixed value over a wide temperature range, wherein the power amplifier is an element of the second current mirror circuit; a temperature compensation circuit connected to the first current mirror circuit for providing temperature compensation therewith; a first reference voltage source connected to the first current mirror circuit by way of the temperature compensation circuit for providing a first reference voltage Vref to the first current mirror circuit; a current sink connected to the first current mirror circuit; a voltage source adjustment circuit connected to the first current mirror circuit for setting a voltage provided to the first current mirror circuit; the first current mirror circuit comprises: a first transistor having a source, a drain and a gate; a second transistor having a gate connected to the drain of the first transistor and a source connected to the gate of the first transistor at a first node; and a fourth transistor having a drain connected to a second reference voltage source and receiving a second reference voltage Vabc, a source connected to ground, and a gate connected to the source of the second transistor and the gate of the first transistor at the first node.

Claim 3

The active bias circuit of claim 1 , wherein the second current mirror circuit comprises: the fourth transistor; a third transistor having a drain connected to the first node, a source connected to the ground and a gate connected to a gate of the power amplifier at a second node; and the power amplifier, wherein the power amplifier has a drain connected to a third reference voltage source and receiving a third reference voltage Vdd and a source connected to the ground.

Claim 4

The active bias circuit of claim 2 , wherein the temperature compensation circuit connected to the first current mirror circuit comprises: a first resistor R 1 having a first terminal connected to the first reference voltage source and a second terminal connected to a drain of the second transistor; and a second resistor R 2 having a first terminal connected to the second terminal of the first resistor R 1 and a second terminal connected to the drain of the first transistor.

Claim 5

The active bias circuit of claim 2 , wherein the current sink comprises the third transistor, which is shared by the first and second current mirror circuits, being connected to the second transistor.

Claim 6

The active bias circuit of claim 2 , wherein the voltage source adjustment circuit comprises a set resistor Rset connected between the source of the first transistor and the ground.

Claim 7

The active bias circuit of claim 2 , further comprising a loading feedback network circuit connected to the second current mirror circuit.

Claim 8

The active bias circuit of claim 6 , wherein the loading feedback network circuit comprises: a feedback resistor Rf having a first terminal connected to the gate of the power amplifier at the second node; and a feedback capacitor Cf connected between a second terminal of the feedback resistor Rf and the ground.

Claim 9

The active bias circuit of claim 7 , further comprising a breakdown voltage enhancement circuit, the breakdown voltage enhancement circuit including: first and second breakdown voltage resistors Rbr 1 , Rbr 2 connected in series between the source of the fourth transistor and the ground, wherein a third node is formed at the connection of the source of the fourth transistor and a terminal of the first breakdown voltage resistor Rbr 1 ; and a breakdown voltage transistor having a drain connected to the fourth transistor and the first breakdown voltage resistor Rbr 1 at the third node, a source connected to the ground, and a gate connected to a fourth node located between the first and second breakdown resistors Rbr 1 , Rbr 2 .

Claim 10

The active bias circuit of claim 8 , further comprising an RF blocking resistor having a first terminal connected to the second node and a second terminal connected to the third node.

Claim 11

The active bias circuit of claim 8 , further comprising a capacitor having a first terminal connected to the third node and a second terminal connected to the ground.

Claim 12

The active bias circuit of claim 8 , further comprising a stabilizing operation circuit connected to the first and second current mirror circuits for stabilizing operations thereof.

Claim 13

The active bias circuit of claim 11 , wherein the stabilizing operation circuit comprises one or more Miller capacitors.

Claim 14

The active bias circuit of claim 11 , wherein the stabilizing operation circuit comprises a plurality of resistors.

Claim 15

The active bias circuit of claim 13 , wherein the plurality of resistors of the stabilizing operation circuit comprises: a first stabilizing resistor RS 1 having a first terminal connected to the first node and a second terminal connected to the gate of the first transistor; a second stabilizing resistor RS 2 having a first terminal connected to the gate of the second transistor and a second terminal connected to the drain of the first transistor and the second terminal of the second resistor R 2 at a fifth node; a third stabilizing resistor RS 3 having a first terminal connected to the gate of the third transistor and a second terminal connected to a sixth node located between the second terminal of the feedback resistor Rf and the feedback capacitor Cf; and a fourth stabilizing resistor RS 4 having a first terminal connected to the first node and a second terminal connected to the gate of the fourth transistor.

Claim 16

An active bias circuit for maintaining a power amplifier DC quiescent current at a fixed value over a wide temperature range, comprising: a first current mirror circuit including a first transistor, a second transistor having a gate connected to a drain of the first transistor and a drain connected to a first reference voltage source for receiving a first reference voltage Vref, and a fourth transistor having a drain connected to a second reference voltage source for receiving a second reference voltage Vabc, and a gate connected to a source of the second transistor and to a gate of the first transistor; a second current mirror circuit including the fourth transistor, a third transistor having a drain connected to the source of the second transistor at a first node, a source connected to ground, and a power amplifier having a drain connected to a third reference voltage source for receiving a third reference voltage Vdd, a source connected to the ground, and a gate connected to a gate of the third transistor at a second node; a temperature compensation circuit including a first resistor R 1 having a first terminal connected to the first reference voltage source and a second terminal connected to the drain of the second transistor, and a second resistor R 2 having a first terminal connected to the second terminal of the first resistor R 1 and a second terminal connected to the drain of the first transistor; and a voltage source adjustment circuit including a set resistor Rset connected between a source of the first transistor and the ground.

Claim 17

An active bias circuit for maintaining a power amplifier DC quiescent current at a fixed value over a wide temperature range, comprising: a first current mirror circuit including a first transistor, a second transistor having a gate connected to a drain of the first transistor and a drain connected to a first reference voltage source for receiving a first reference voltage Vref, and a fourth transistor having a drain connected to a second reference voltage source for receiving a second reference voltage Vabc, and a gate connected to a source of the second transistor and to a gate of the first transistor; a second current mirror circuit including the fourth transistor, a third transistor having a drain connected to the source of the second transistor at a first node, a source connected to ground, and a power amplifier having a drain connected to a third reference voltage source for receiving a third reference voltage Vdd, a source connected to the ground, and a gate connected to a gate of the third transistor at a second node; a temperature compensation circuit including a first resistor R 1 having a first terminal connected to the first reference voltage source and a second terminal connected to the drain of the second transistor, and a second resistor R 2 having a first terminal connected to the second terminal of the first resistor R 1 and a second terminal connected to the drain of the first transistor; and a voltage source adjustment circuit including a set resistor Rset connected between a source of the first transistor and the ground.

Claim 18

The active bias circuit of claim 15 , further comprising a loading feedback network circuit connected to the second current mirror circuit.

Claim 19

The active bias circuit of claim 16 , wherein the loading feedback network circuit comprises: a feedback resistor Rf having a first terminal connected to the gate of the power amplifier at the second node and a second terminal connected to the gate of the third transistor; and a feedback capacitor Cf connected between the second terminal of the feedback resistor Rf and the ground.

Claim 20

The active bias circuit of claim 17 , further comprising a breakdown voltage enhancement circuit, the breakdown voltage enhancement circuit including: first and second breakdown voltage resistors Rbr 1 , Rbr 2 connected in series between the source of the fourth transistor and the ground, wherein a third node is formed at the connection of the source of the fourth transistor and a terminal of the first breakdown voltage resistor Rbr 1 ; and a breakdown voltage transistor having a drain connected to the source of the fourth transistor and the first breakdown voltage resistor Rbr 1 at the third node, a source connected to the ground, and a gate connected to a fourth node located between the first and second breakdown resistors Rbr 1 , Rbr 2 .

Claim 21

The active bias circuit of claim 18 , further comprising an RF blocking resistor Rb having a first terminal connected to the second node and a second terminal connected to the third node.

Claim 22

The active bias circuit of claim 18 , further comprising a capacitor having a first terminal connected to the third node and a second terminal connected to the ground.

Claim 23

The active bias circuit of claim 18 , further comprising a stabilizing operation circuit, the stabilizing operation circuit including: a first stabilizing resistor RS 1 having a first terminal connected to the first node and a second terminal connected to the gate of the first transistor; a second stabilizing resistor RS 2 having a first terminal connected to the gate of the second transistor and a second terminal connected to the drain of the first transistor and the second terminal of the second resistor R 2 at a fifth node; a third stabilizing resistor RS 3 having a first terminal connected to the gate of the third transistor and a second terminal connected to a sixth node located between the second terminal of the feedback resistor Rf and the feedback capacitor Cf; and a fourth stabilizing resistor RS 4 having a first terminal connected to the first node and a second terminal connected to the gate of the fourth transistor.