Magnetic memory device

Claim 2

A magnetic memory device comprising: a memory cell assembled by first and second tunnel junction portions and a cell selection semiconductor element, each of said first and second tunnel junction portions being formed of a stack of a pinned layer in which a magnetization direction is fixed and a recording layer in which a magnetization direction changes depending on an external magnetic field, said stack having single or multiple tunnel junctions, said first tunnel junction section having a first end and a second end opposed to each other in the stacking direction, said second tunnel junction portion having a third end and a fourth end opposed to each other in the stacking direction; a first data line connected to said first end of said first tunnel junction section; a second data line connected to said third end of said second tunnel junction section; and a bit line connected to said second end of said first tunnel junction portion and said fourth end of said second tunnel junction section via said cell selection semiconductor element.

Claim 3

A magnetic memory device according to claim 1 , further comprising: a first write line disposed at said first end of said first tunnel junction section; a second write line disposed at said third end of said second tunnel junction section; and a third write line disposed at said first end or said second end of said first tunnel junction section and at said third end or said fourth end of said second tunnel junction portion.

Claim 4

A magnetic memory device according to claim 2 , wherein said first tunnel junction section is disposed in the same plane as that of said second tunnel junction section, said first write line is disposed in parallel to said second write line in the same plane, and said third write line crosses the second write line in the vicinity of said first and second tunnel junction sections, and a current direction that flows said first write line is opposite to a current direction that flows said second write line.

Claim 5

A magnetic memory device according to claim 2 , wherein said first tunnel junction section is disposed in a direction vertical to said second tunnel junction section, said first write line and said second write line are disposed in parallel in a vertical direction, and said third write line crosses the second write line in the vicinity of said first and second tunnel junction sections, and a current direction that flows said first write line is opposite to a current direction that flows said second write line.

Claim 6

A magnetic memory device according to claim 1 , wherein said first and second tunnel junction sections are equal to each other in a resistance value and a magneto resistance ratio, and have magnetization directions of said recording layers in said sections which are always kept in an anti-parallel each other.

Claim 7

A magnetic memory device according to claim 1 , wherein one of said first tunnel junction section and said second tunnel junction section has a resistance lower than the other.

Claim 8

A magnetic memory device according to claim 1 , wherein, when a potential difference is applied between each of said first data line connected to said first tunnel junction section and said second data line connected to said second tunnel junction section and said bit line, the magnitudes of qualities of currents that flow said first and second data lines are compared with each other, to discriminate the stored information.

Claim 9

A magnetic memory device according to claim 1 , wherein, when a potential difference is applied between said first data line connected to said first tunnel junction section and said second data line connected to said second tunnel junction section, a reference potential and a voltage that appears in said bit line are compared with each other, to discriminate the stored information.

Claim 10

A magnetic memory device comprising: a magnetic memory cell array comprised of a plurality of divided memory cell arrays each having a plurality of magnetic memory cells, first and second data lines, a plurality of word lines crossing said first and/or second data lines, and a plurality of bit lines crossing said first and/or second data lines, wherein each of said magnetic memory cells is fabricated by first and second tunnel junction sections and a cell selection semiconductor element, each of said first and second tunnel junction sections being formed of a stack of a pinned layer having a magnetization direction fixed and a recording layer in which a magnetic direction changes depending on an external magnetic field, said stack has single or multiple tunnel junctions, said first tunnel junction section has a first end and a second end opposite to each other in the stacking direction, said second tunnel junction section has a third end and a fourth end opposite to each other in the stacking direction, said first end of said first tunnel junction section is connected to said first data line, said third end of said second tunnel junction section is connected to said second data line, said second end of said first tunnel junction section and said fourth end of said second tunnel junction section are connected to said bit line via said cell selection semiconductor element.

Claim 11

A magnetic memory device comprising: a magnetic memory cell array comprised of a plurality of divided memory cell arrays each having a plurality of magnetic memory cells, first and second data lines, a plurality of word lines crossing said first and/or second data lines, and a plurality of bit lines crossing said first and/or second data lines, wherein each of said magnetic memory cells is fabricated by first and second tunnel junction sections and a cell selection semiconductor element, each of said first and second tunnel junction sections being formed of a stack of a pinned layer having a magnetization direction fixed and a recording layer in which a magnetic direction changes depending on an external magnetic field, said stack has single or multiple tunnel junctions, said first tunnel junction section has a first end and a second end opposite to each other in the stacking direction, said second tunnel junction section has a third end and a fourth end opposite to each other in the stacking direction, said first end of said first tunnel junction section is connected to said first data line, said third end of said second tunnel junction section is connected to said second data line, said second end of said first tunnel junction section and said fourth end of said second tunnel junction section are connected to said bit line via said cell selection semiconductor element.

Claim 12

A magnetic memory device according to claim 9 , wherein said first and second data lines are divided in a plurality of first and second subsidiary data lines, and said first end of said first tunnel junction section of each of said divided memory arrays is connected to a corresponding one of said first subsidiary data lines and said third end of said second tunnel junction section of each of said divided memory arrays is connected to a corresponding one of said second subsidiary data lines.

Claim 13

A magnetic memory device according to claim 9 , wherein said first and second data lines are arranged in parallel.

Claim 14

A magnetic memory device according to claim 9 , wherein said first and second data lines cross to each other.

Claim 15

A magnetic memory device comprising: a magnetic memory cell array comprised of a plurality of divided memory cell arrays, each having a plurality of magnetic memory cells, first and second data lines, a plurality of word lines crossing said first and/or second data lines, a plurality of bit lines arranged in parallel with said first and/or second data lines, wherein each of said magnetic memory cells is fabricated by first and second tunnel junction sections and a cell selection semiconductor element, each of said first and second tunnel junction portions is formed of a stack of a pinned layer having a magnetization direction fixed and a record layer in which a magnetic direction changes depending on an external magnetic field, said stack has single or multiple tunnel junctions, said first tunnel junction section has a first end and a second end opposite to each other in the stacking direction, said second tunnel junction portion has a third end and a fourth end opposite to each other in the stacking direction, said first end of said first tunnel junction section is connected to said first data line, said third end of said second tunnel junction section is connected to said second data line, said second end of said first tunnel junction portion and said fourth end of said second tunnel junction portion are connected to said bit line via said cell selection semiconductor element.

Claim 16

A magnetic memory device comprising: a magnetic memory cell array comprised of a plurality of divided memory cell arrays, each having a plurality of magnetic memory cells, first and second data lines, a plurality of word lines crossing said first and/or second data lines, a plurality of bit lines arranged in parallel with said first and/or second data lines, wherein each of said magnetic memory cells is fabricated by first and second tunnel junction sections and a cell selection semiconductor element, each of said first and second tunnel junction portions is formed of a stack of a pinned layer having a magnetization direction fixed and a record layer in which a magnetic direction changes depending on an external magnetic field, said stack has single or multiple tunnel junctions, said first tunnel junction section has a first end and a second end opposite to each other in the stacking direction, said second tunnel junction portion has a third end and a fourth end opposite to each other in the stacking direction, said first end of said first tunnel junction section is connected to said first data line, said third end of said second tunnel junction section is connected to said second data line, said second end of said first tunnel junction portion and said fourth end of said second tunnel junction portion are connected to said bit line via said cell selection semiconductor element.

Claim 17

A magnetic memory device according to claim 13 , wherein said first and second data lines are divided in a plurality of first and second subsidiary data lines, and said first end of said first tunnel junction section of each of said divided memory arrays is connected to a corresponding one of said first subsidiary data lines and said third end of said second tunnel junction section of each of said divided memory arrays is connected to a corresponding one of said second subsidiary data lines.

Claim 18

A magnetic memory device according to claim 13 , wherein said first and second data lines are arranged in parallel.

Claim 19

A magnetic memory device according to claim 13 , said first and second data lines cross to each other.

Claim 20

A magnetic memory device comprising: a magnetic memory cell array comprised of a plurality of divided memory cell arrays, each of said divided memory cell arrays being fabricated by a plurality of magnetic memory cells, first and second subsidiary data lines disposed in parallel to each other, a plurality of word lines crossing said first and/or second data lines, and a plurality of subsidiary bit lines parallel to said first and second data lines, wherein each of said magnetic memory cells is formed of first and second tunnel junction section and a cell selection semiconductor element, each of said first and second tunnel junction section comprises a stack of a pinned layer having a magnetization layer pinned therein and a record layer in which a magnetization direction changes depending on an external magnetization field, said first tunnel junction section has a first end and a second end opposite to each other in the stacking direction, said second tunnel junction section has a third end and a fourth end opposite to each other in the stacking direction, said first end of said first tunnel junction section is connected to said first subsidiary data line, said third end of said second tunnel junction section is connected to said second subsidiary data line, said second end of said first tunnel junction portion and said fourth end of said second tunnel junction section are connected to a corresponding one of said subsidiary bit lines, said magnetic memory device has a plurality of selection transistors for selectively connecting said first and second subsidiary data lines, said subsidiary bit lines, first and second data lines, and a bit line.

Claim 21

A magnetic memory device comprising: a magnetic memory cell array comprised of a plurality of divided memory cell arrays, each of said divided memory cell arrays being fabricated by a plurality of magnetic memory cells, first and second subsidiary data lines disposed in parallel to each other, a plurality of word lines crossing said first and/or second data lines, and a plurality of subsidiary bit lines parallel to said first and second data lines, wherein each of said magnetic memory cells is formed of first and second tunnel junction section and a cell selection semiconductor element, each of said first and second tunnel junction section comprises a stack of a pinned layer having a magnetization layer pinned therein and a record layer in which a magnetization direction changes depending on an external magnetization field, said first tunnel junction section has a first end and a second end opposite to each other in the stacking direction, said second tunnel junction section has a third end and a fourth end opposite to each other in the stacking direction, said first end of said first tunnel junction section is connected to said first subsidiary data line, said third end of said second tunnel junction section is connected to said second subsidiary data line, said second end of said first tunnel junction portion and said fourth end of said second tunnel junction section are connected to a corresponding one of said subsidiary bit lines, said magnetic memory device has a plurality of selection transistors for selectively connecting said first and second subsidiary data lines, said subsidiary bit lines, first and second data lines, and a bit line.

Claim 22

A magnetic memory device according to claim 17 , wherein said semiconductor element is formed of a diode, and when a potential difference is applied between said first data line connected to said first tunnel junction section and said second data line connected to said second tunnel junction section via said diode, the magnitudes relevant to a reference potential of a voltage that appears in said bit line are compared with each other, to discriminate the stored information.

Claim 23

A magnetic memory device comprising: a magnetic memory cell array comprised of a plurality of divided memory cell arrays each having a plurality of magnetic memory cells, first and second data lines crossing to each other; a plurality of word lines and a plurality of bit lines crossing to each other; wherein each of said magnetic memory cells is fabricated by first and second tunnel junction sections and a cell selection semiconductor element, each of said first and second tunnel junction sections being formed of a stack of a pinned layer having a magnetization direction pinned therein and a record layer in which a magnetic direction changes depending on an external magnetic field, said stack has single or multiple tunnel junctions, said first tunnel junction portion has a first end and a second end opposite to each other in the stacking direction, said second tunnel junction portion has a third end and a fourth end opposite to each other in the stacking direction, said first end of said first tunnel junction section is connected to said first data line, said third end of said second tunnel junction section is connected to said second data line, said second end of said first tunnel junction section and said fourth end of said second tunnel junction section are connected to said bit line via said cell selection semiconductor element.

Claim 24

A magnetic memory device comprising: a magnetic memory cell array comprised of a plurality of divided memory cell arrays each having a plurality of magnetic memory cells, first and second data lines crossing to each other; a plurality of word lines and a plurality of bit lines crossing to each other; wherein each of said magnetic memory cells is fabricated by first and second tunnel junction sections and a cell selection semiconductor element, each of said first and second tunnel junction sections being formed of a stack of a pinned layer having a magnetization direction pinned therein and a record layer in which a magnetic direction changes depending on an external magnetic field, said stack has single or multiple tunnel junctions, said first tunnel junction portion has a first end and a second end opposite to each other in the stacking direction, said second tunnel junction portion has a third end and a fourth end opposite to each other in the stacking direction, said first end of said first tunnel junction section is connected to said first data line, said third end of said second tunnel junction section is connected to said second data line, said second end of said first tunnel junction section and said fourth end of said second tunnel junction section are connected to said bit line via said cell selection semiconductor element.

Claim 25

A magnetic memory device according to claim 19 , wherein said first and second data lines are divided in a plurality of first and second subsidiary data lines, and said first end of said first tunnel junction section of each of said divided memory arrays is connected to a corresponding one of said first subsidiary data lines and said third end of said second tunnel junction section of each of said divided memory arrays is connected to a corresponding one of said second subsidiary data lines.

Claim 26

A magnetic memory device comprising: a tunnel junction section including: a stack of a first pinned layer having a magnetization direction fixed, a first tunnel barrier adjacent to said first pinned layer, a first magnetic layer which is opposite to said first pinned layer via said first tunnel barrier and in which a magnetization direction changes depending on an external magnetic field, a second magnetic layer which is anti-ferromagnetically coupled to said first ferromagnetic layer and in which a magnetization direction changes depending on the external magnetic field, and a non-magnetic conductive layer interposed between said first and second magnetic layers, for anti-ferromagnetically coupling between said first and second magnetic layers, a second tunnel barrier adjacent to said second magnetic layer and a second pinned layer opposite to said second magnetic layer via said second tunnel barrier and a detection section configured to detect a current difference between a first tunnel current flowing across said first magnetic layer and said first pinned layer and a second tunnel current flowing across said second magnetic layer and said second pinned layer or a load voltage difference in a differential scheme.

Claim 27

A magnetic memory device comprising: a tunnel junction section including: a stack of a first pinned layer having a magnetization direction fixed, a first tunnel barrier adjacent to said first pinned layer, a first magnetic layer which is opposite to said first pinned layer via said first tunnel barrier and in which a magnetization direction changes depending on an external magnetic field, a second magnetic layer which is anti-ferromagnetically coupled to said first ferromagnetic layer and in which a magnetization direction changes depending on the external magnetic field, and a non-magnetic conductive layer interposed between said first and second magnetic layers, for anti-ferromagnetically coupling between said first and second magnetic layers, a second tunnel barrier adjacent to said second magnetic layer and a second pinned layer opposite to said second magnetic layer via said second tunnel barrier and a detection section configured to detect a current difference between a first tunnel current flowing across said first magnetic layer and said first pinned layer and a second tunnel current flowing across said second magnetic layer and said second pinned layer or a load voltage difference in a differential scheme.

Claim 28

A magnetic memory device comprising: a tunnel junction including: a stack of a first pinned layer having a magnetization direction fixed, a first tunnel barrier adjacent to said first pinned layer, a first magnetic layer which is opposite to said first pinned layer via said first tunnel barrier and in which a magnetization direction changes depending on an external magnetic field, a second magnetic layer which is anti-ferromagnetically coupled to said first ferromagnetic layer and in which a magnetization direction changes depending on the external magnetic field, and a non-magnetic conductive layer interposed between said first and second magnetic layers, a second tunnel barrier adjacent to said second magnetic layer and a second pinned layer opposite to said second magnetic layer via said second tunnel barrier, a bit line electrically connected to all or either of said first magnetic layer, said non-magnetic conductive layer, and said second magnetic layer; a first data line electrically connected to said first pinned layer; and a second data line electrically connected to said second pinned layer.

Claim 29

A magnetic memory device comprising: a tunnel junction including: a stack of a first pinned layer having a magnetization direction fixed, a first tunnel barrier adjacent to said first pinned layer, a first magnetic layer which is opposite to said first pinned layer via said first tunnel barrier and in which a magnetization direction changes depending on an external magnetic field, a second magnetic layer which is anti-ferromagnetically coupled to said first ferromagnetic layer and in which a magnetization direction changes depending on the external magnetic field, and a non-magnetic conductive layer interposed between said first and second magnetic layers, a second tunnel barrier adjacent to said second magnetic layer and a second pinned layer opposite to said second magnetic layer via said second tunnel barrier, a bit line electrically connected to all or either of said first magnetic layer, said non-magnetic conductive layer, and said second magnetic layer; a first data line electrically connected to said first pinned layer; and a second data line electrically connected to said second pinned layer.

Claim 30

A magnetic memory device according to claim 22 , further comprising a detection section configured to detect a current difference between a first tunnel current flowing across said first magnetic layer and said first pinned layer and a second tunnel current flowing across said second magnetic layer and said second pinned layer or a load voltage difference in a differential scheme.

Claim 31

A magnetic memory device according to claim 22 , which includes an electrode layer formed on one of said first pinned layer and said second pinned layer which is separated from a main surface of a substrate, for electrically connecting said bit line and all or either of said first magnetic layer, said non-magnetic conductive layer, and said second magnetic layer.

Claim 32

A magnetic memory device according to claim 22 , wherein said first and second ferromagnetic layers differ in thickness from each other.

Claim 33

A magnetic memory device according to claim 22 , wherein said first and second ferromagnetic layers are made of magnetic materials different from each other in magnetic moment, respectively.